Inicio Interfaz I2C & I3C ICs I2C & I3C level shifters, buffers & hubs

Búfer/repetidor I2C/SMBus de 2 bits con traslación de nivel a 400 kHz

PCA9517 no se recomienda para nuevos diseños
Aunque esta producto sigue en producción para dar soporte a diseños anteriores, no lo recomendamos para nuevos diseños. Considere una de estas alternativas:
open-in-new Comparar alternativas
Funcionalidad similar a la del dispositivo comparado
TCA9517 ACTIVO Repetidor/búfer de I2C kHz/SMBus de 2 bits de traducción de nivel 400 con alta impedancia apagada The TCA9517 addresses the application usage limitations as specified in the PCA9517 datasheet

Detalles del producto

Frequency (max) (MHz) 0.4 VCCA (min) (V) 0.9 VCCA (max) (V) 5.5 VCCB (min) (V) 2.7 VCCB (max) (V) 5.5 Supply restrictions No rule Rating Catalog Operating temperature range (°C) -40 to 85
Frequency (max) (MHz) 0.4 VCCA (min) (V) 0.9 VCCA (max) (V) 5.5 VCCB (min) (V) 2.7 VCCB (max) (V) 5.5 Supply restrictions No rule Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 8 29.4 mm² 4.9 x 6 VSSOP (DGK) 8 14.7 mm² 3 x 4.9
  • Two-Channel Bidirectional Buffer
  • I2C Bus and SMBus Compatible
  • Operating Supply Voltage Range of 0.9 V to 5.5 V on A Side
  • Operating Supply Voltage Range of 2.7 V to 5.5 V on B Side
  • Voltage-Level Translation From 0.9 V to 5.5 V and 2.7 V to 5.5 V
  • Footprint and Function Replacement for PCA9515A
  • Active-High Repeater-Enable Input
  • Open-Drain I2C I/O
  • 5.5-V Tolerant I2C and Enable Input Support Mixed-Mode Signal Operation
  • Lockup-Free Operation
  • Accommodates Standard Mode and Fast Mode I2C Devices and Multiple Masters
  • Powered-Off High-Impedance I2C Pins
  • 400-kHz Fast I2C Bus
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

All trademarks are the property of their respective owners.

  • Two-Channel Bidirectional Buffer
  • I2C Bus and SMBus Compatible
  • Operating Supply Voltage Range of 0.9 V to 5.5 V on A Side
  • Operating Supply Voltage Range of 2.7 V to 5.5 V on B Side
  • Voltage-Level Translation From 0.9 V to 5.5 V and 2.7 V to 5.5 V
  • Footprint and Function Replacement for PCA9515A
  • Active-High Repeater-Enable Input
  • Open-Drain I2C I/O
  • 5.5-V Tolerant I2C and Enable Input Support Mixed-Mode Signal Operation
  • Lockup-Free Operation
  • Accommodates Standard Mode and Fast Mode I2C Devices and Multiple Masters
  • Powered-Off High-Impedance I2C Pins
  • 400-kHz Fast I2C Bus
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

All trademarks are the property of their respective owners.

This dual bidirectional I2C buffer is operational at 2.7 V to 5.5 V.

The PCA9517 is a BiCMOS integrated circuit intended for I2C bus and SMBus systems. It can also provide bidirectional voltage-level translation (up-translation/down-translation) between low voltages (down to 0.9 V) and higher voltages (2.7 V to 5.5 V) in mixed-mode applications. This device enables I2C and similar bus systems to be extended, without degradation of performance even during level shifting.

The PCA9517 buffers both the serial data (SDA) and the serial clock (SCL) signals on the I2C bus, thus allowing two buses of 400-pF bus capacitance to be connected in an I2C application. This device can also be used to isolate two halves of a bus for voltage and capacitance.

The PCA9517 has two types of drivers—A-side drivers and B-side drivers. All inputs and I/Os are overvoltage tolerant to 5.5 V, even when the device is unpowered (VCCB and/or VCCA = 0 V).

The PCA9517 doesnot support clock stretching and arbitration across the repeater.

The B-side drivers operate from 2.7 V to 5.5 V and behave like the drivers in the PCA9515A. The output low level for this internal buffer is approximately 0.5 V, but the input voltage must be 70 mV or more below the output low level when the output internally is driven low. The higher-voltage low signal is called a buffered low. When the B-side I/O is driven low internally, the low is not recognized as a low by the input. This feature prevents a lockup condition from occurring when the input low condition is released.

This type of design on the B side prevents it from being used in series with the PCA9515A and another PCA9517 (B side). This is because these devices do not recognize buffered low signals as a valid low and do not propagate it as a buffered low again.

The A-side drivers operate from 0.9 V to 5.5 V and drive more current. They do not require the buffered low feature (or the static offset voltage). This means that a low signal on the B side translates to a nearly 0-V low on the A side, which accommodates smaller voltage swings of lower-voltage logic. The output pulldown on the A side drives a hard low, and the input level is set at 0.3 VCCA to accommodate the need for a lower low level in systems where the low-voltage-side supply voltage is as low as 0.9 V.

The A side of two or more PCA9517s can be connected together to allow a star topography, with the A side on the common bus. Also, the A side can be connected directly to any other buffer with static- or dynamic-offset voltage. Multiple PCA9517s can be connected in series, A side to B side, with no buildup in offset voltage and with only time-of-flight delays to consider.

The PCA9517 drivers are enabled when VCCA is above 0.8 V and VCCB is above 2.5 V.

The PCA9517 has an active-high enable (EN) input with an internal pullup to VCCB, which allows the user to select when the repeater is active. This can be used to isolate a badly behaved slave on power-up reset. It should never change state during an I2C operation, because disabling during a bus operation hangs the bus, and enabling part way through a bus cycle could confuse the I2C parts being enabled. The EN input should change state only when the global bus and repeater port are in an idle state, to prevent system failures.

The PCA9517 includes a power-up circuit that keeps the output drivers turned off until VCCB is above 2.5 V and the VCCA is above 0.8 V. VCCB and VCCA can be applied in any sequence at power up. After power up and with the EN high, a low level on the A side (below 0.3 VCCA) turns the corresponding B-side driver (either SDA or SCL) on and drives the B side down to approximately 0.5 V. When the A side rises above 0.3 VCCA, the B-side pulldown driver is turned off and the external pullup resistor pulls the pin high. When the B side falls first and goes below 0.3 VCCB, the A-side driver is turned on and the A side pulls down to 0 V. The B-side pulldown is not enabled unless the B-side voltage goes below 0.4 V. If the B-side low voltage does not go below 0.5 V, the A-side driver turns off when the B-side voltage is above 0.7 VCCB. If the B-side low voltage goes below 0.4 V, the B-side pulldown driver is enabled, and the B side is able to rise to only 0.5 V until the A side rises above 0.3 VCCA. Then the B side continues to rise, being pulled up by the external pullup resistor. VCCA is only used to provide the 0.3 VCCA reference to the A-side input comparators and for the power-good-detect circuit. The PCA9517 logic and all I/Os are powered by the VCCB pin.

As with the standard I2C system, pullup resistors are required to provide the logic-high levels on the buffered bus. The PCA9517 has standard open-collector configuration of the I2C bus. The size of these pullup resistors depends on the system, but each side of the repeater must have a pullup resistor. The device is designed to work with Standard mode and Fast mode I2C devices in addition to SMBus devices. Standard mode I2C devices only specify 3 mA in a generic I2C system, where Standard mode devices and multiple masters are possible. Under certain conditions, higher termination currents can be used.

This dual bidirectional I2C buffer is operational at 2.7 V to 5.5 V.

The PCA9517 is a BiCMOS integrated circuit intended for I2C bus and SMBus systems. It can also provide bidirectional voltage-level translation (up-translation/down-translation) between low voltages (down to 0.9 V) and higher voltages (2.7 V to 5.5 V) in mixed-mode applications. This device enables I2C and similar bus systems to be extended, without degradation of performance even during level shifting.

The PCA9517 buffers both the serial data (SDA) and the serial clock (SCL) signals on the I2C bus, thus allowing two buses of 400-pF bus capacitance to be connected in an I2C application. This device can also be used to isolate two halves of a bus for voltage and capacitance.

The PCA9517 has two types of drivers—A-side drivers and B-side drivers. All inputs and I/Os are overvoltage tolerant to 5.5 V, even when the device is unpowered (VCCB and/or VCCA = 0 V).

The PCA9517 doesnot support clock stretching and arbitration across the repeater.

The B-side drivers operate from 2.7 V to 5.5 V and behave like the drivers in the PCA9515A. The output low level for this internal buffer is approximately 0.5 V, but the input voltage must be 70 mV or more below the output low level when the output internally is driven low. The higher-voltage low signal is called a buffered low. When the B-side I/O is driven low internally, the low is not recognized as a low by the input. This feature prevents a lockup condition from occurring when the input low condition is released.

This type of design on the B side prevents it from being used in series with the PCA9515A and another PCA9517 (B side). This is because these devices do not recognize buffered low signals as a valid low and do not propagate it as a buffered low again.

The A-side drivers operate from 0.9 V to 5.5 V and drive more current. They do not require the buffered low feature (or the static offset voltage). This means that a low signal on the B side translates to a nearly 0-V low on the A side, which accommodates smaller voltage swings of lower-voltage logic. The output pulldown on the A side drives a hard low, and the input level is set at 0.3 VCCA to accommodate the need for a lower low level in systems where the low-voltage-side supply voltage is as low as 0.9 V.

The A side of two or more PCA9517s can be connected together to allow a star topography, with the A side on the common bus. Also, the A side can be connected directly to any other buffer with static- or dynamic-offset voltage. Multiple PCA9517s can be connected in series, A side to B side, with no buildup in offset voltage and with only time-of-flight delays to consider.

The PCA9517 drivers are enabled when VCCA is above 0.8 V and VCCB is above 2.5 V.

The PCA9517 has an active-high enable (EN) input with an internal pullup to VCCB, which allows the user to select when the repeater is active. This can be used to isolate a badly behaved slave on power-up reset. It should never change state during an I2C operation, because disabling during a bus operation hangs the bus, and enabling part way through a bus cycle could confuse the I2C parts being enabled. The EN input should change state only when the global bus and repeater port are in an idle state, to prevent system failures.

The PCA9517 includes a power-up circuit that keeps the output drivers turned off until VCCB is above 2.5 V and the VCCA is above 0.8 V. VCCB and VCCA can be applied in any sequence at power up. After power up and with the EN high, a low level on the A side (below 0.3 VCCA) turns the corresponding B-side driver (either SDA or SCL) on and drives the B side down to approximately 0.5 V. When the A side rises above 0.3 VCCA, the B-side pulldown driver is turned off and the external pullup resistor pulls the pin high. When the B side falls first and goes below 0.3 VCCB, the A-side driver is turned on and the A side pulls down to 0 V. The B-side pulldown is not enabled unless the B-side voltage goes below 0.4 V. If the B-side low voltage does not go below 0.5 V, the A-side driver turns off when the B-side voltage is above 0.7 VCCB. If the B-side low voltage goes below 0.4 V, the B-side pulldown driver is enabled, and the B side is able to rise to only 0.5 V until the A side rises above 0.3 VCCA. Then the B side continues to rise, being pulled up by the external pullup resistor. VCCA is only used to provide the 0.3 VCCA reference to the A-side input comparators and for the power-good-detect circuit. The PCA9517 logic and all I/Os are powered by the VCCB pin.

As with the standard I2C system, pullup resistors are required to provide the logic-high levels on the buffered bus. The PCA9517 has standard open-collector configuration of the I2C bus. The size of these pullup resistors depends on the system, but each side of the repeater must have a pullup resistor. The device is designed to work with Standard mode and Fast mode I2C devices in addition to SMBus devices. Standard mode I2C devices only specify 3 mA in a generic I2C system, where Standard mode devices and multiple masters are possible. Under certain conditions, higher termination currents can be used.

Descargar Ver vídeo con transcripción Video

Documentación técnica

star =Principal documentación para este producto seleccionada por TI
No se encontraron resultados. Borre su búsqueda y vuelva a intentarlo.
Ver todo 6
Tipo Título Fecha
* Data sheet Level-Translating I2C Bus Repeater datasheet (Rev. E) 12 jun 2014
Selection guide Logic Guide (Rev. AB) 12 jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 dic 2015
Application note Troubleshooting I2C Bus Protocol 19 oct 2009
Application note Programming Fun Lights With TI's TCA6507 30 nov 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 jul 2004

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Modelo de simulación

PCA9517 IBIS Model (Rev. A)

SCPM013A.ZIP (59 KB) - IBIS Model
Herramienta de simulación

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Herramienta de simulación

TINA-TI — Programa de simulación analógica basado en SPICE

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
Guía del usuario: PDF
Diseños de referencia

TIDA-00090 — Diseño de referencia de audio USB

This reference design, featuring the TLV320AIC3256 audio codec, is a fully-functional USB powered streaming audio platform that allows external audio sources to be connected to the USB port of a PC or laptop. User control is provided via a powerful, easy-to-use Windows-based GUI.

Software (...)

Test report: PDF
Esquema: PDF
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
SOIC (D) 8 Ultra Librarian
VSSOP (DGK) 8 Ultra Librarian

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

Soporte y capacitación

Foros de TI E2E™ con asistencia técnica de los ingenieros de TI

El contenido lo proporcionan “tal como está” TI y los colaboradores de la comunidad y no constituye especificaciones de TI. Consulte los términos de uso.

Si tiene preguntas sobre la calidad, el paquete o el pedido de productos de TI, consulte el soporte de TI. ​​​​​​​​​​​​​​

Videos