CD74HC08-EP
- Controlled Baseline
- One Assembly/Test Site, One Fabrication Site
- Extended Temperature Performance of –55°C to 125°C
- Enhanced Diminishing Manufacturing Sources (DMS) Support
- Enhanced Product-Change Notification
- Qualification Pedigree
- Buffered Inputs
- Typical Propagation Delay 7 ns at VCC = 5 V, CL = 15 pF, TA = 25°C
- Fanout (Over Temperature Range)
- Standard Outputs ... 10 LSTTL Loads
- Bus Driver Outputs ... 15 LSTTL Loads
- Balanced Propagation Delay and Transition Times
- Significant Power Reduction Compared to LSTTL Logic ICs
- 2-V to 6-V VCC Operation
- High Noise Immunity NIL or NIH = 30% of VCC at VCC = 5 V
- CMOS Input Compatibility, Il
1 µA at VOL, VOH
Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
The CD74HC08 logic gates utilize silicon-gate CMOS technology to achieve operating speeds similar to LSTTL gates, with the low power consumption of standard CMOS integrated circuits. All devices can drive 10 LSTTL loads.
技術資料
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| 上位の文書 | タイプ | タイトル | フォーマットオプション | 最新の英語版をダウンロード | 日付 | |
|---|---|---|---|---|---|---|
| * | データシート | CD74HC08-EP データシート (Rev. B) | 2004/04/07 | |||
| * | VID | CD74HC08-EP VID V6204704 | 2016/06/21 |