DS10BR150
- DC - 1.0 Gbps Low Jitter, High Noise Immunity, Low Power Operation
- On-chip 100Ω Input and Output Termination Minimizes Insertion and Return Losses, Reduces Component Count and Minimizes Board Space
- 7 kV ESD on LVDS I/O Pins Protects Adjoining Components
- Small 3 mm x 3 mm 8-WSON Space Saving Package
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The DS10BR150 is a single channel 1.0 Gbps LVDS buffer optimized for high-speed signal transmission over lossy FR-4 printed circuit board backplanes and balanced cables. Fully differential signal paths ensure exceptional signal integrity and noise immunity.
Wide input common mode range allows the receiver to accept signals with LVDS, CML and LVPECL levels; the output levels are LVDS. A very small package footprint requires a minimal space on the board while the flow-through pinout allows easy board layout. The differential inputs and outputs are internally terminated with a 100Ω resistor to lower device input and output return losses, reduce component count and further minimize board space.
技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | DS10BR150 1.0 Gbps LVDS Buffer / Repeater datasheet (Rev. D) | 2013年 4月 12日 | |
User guide | 1.06 Gbps LVDS Buffer Repeater (DS10BR150) Evaluation Kit | 2012年 1月 25日 |
設計與開發
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DS10BR150EVK — 1.06 Gbps LVDS 緩衝器中繼器 (DS10BR150) 評估套件
The DS10BR150EVK is an evaluation kit designed for demonstrating performance of the 1.06 Gbps LVDS Buffer / Repeater (DS10BR150). The purpose of this document is to: familiarize you with the DS10BR150EVK, suggest the test setup procedures and instrumentation, and guide you through some typical (...)
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
TINA-TI — 基於 SPICE 的類比模擬程式
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
WSON (NGQ) | 8 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。