DS26C32AT
- CMOS Design for Low Power
- ±0.2V Sensitivity over Input Common Mode Voltage Range
- Typical Propagation Delays: 19 ns
- Typical Input hysteresis: 60 mV
- Inputs Won't Load Line When VCC = 0V
- Meets the Requirements of EIA Standard RS-422
- TRI-STATE Outputs for Connection to System Buses
- Available in Surface Mount
- Mil-Std-883C Compliant
All trademarks are the property of their respective owners.
The DS26C32A is a quad differential line receiver designed to meet the RS-422, RS-423, and Federal Standards 1020 and 1030 for balanced and unbalanced digital data transmission, while retaining the low power characteristics of CMOS.
The DS26C32A has an input sensitivity of 200 mV over the common mode input voltage range of ±7V. The DS26C32A features internal pull-up and pull-down resistors which prevent output oscillation on unused channels.
The DS26C32A provides an enable and disable function common to all four receivers. It also features TRI-STATE outputs with 6 mA source and sink capability. This product is pin compatible with the DS26LS32A and the AM26LS32.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | DS26C32AT/DS26C32AM Quad Differential Line Receiver datasheet (Rev. C) | 2013/4/15 | |||
| 應用說明 | AN-903 A Comparison of Differential Termination Techniques (Rev. B) | 2013/4/26 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SOIC (D) | 16 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。