DS90CF384A
- 20 to 65 MHz Shift Clock Support
- 50% Duty Cycle on Receiver Output Clock
- Best-in-Class Set & Hold Times on RxOUTPUTs
- Rx Power Consumption <142 mW (typ) @65MHz Grayscale
- Rx Power-down Mode <200μW (max)
- ESD Rating >7 kV (HBM), >700V (EIAJ)
- Supports VGA, SVGA, XGA and Dual Pixel SXGA.
- PLL Requires no External Components
- Compatible with TIA/EIA-644 LVDS Standard
- Low Profile 56-lead or 48-lead Packages
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The DS90CF384A receiver converts the four LVDS data streams (Up to 1.8 Gbps throughput or 227 Megabytes/sec bandwidth) back into parallel 28 bits of CMOS/TTL data (24 bits of RGB and 4 bits of Hsync, Vsync, DE and CNTL). Also available is the DS90CF364A that converts the three LVDS data streams (Up to 1.3 Gbps throughput or 170 Megabytes/sec bandwidth) back into parallel 21 bits of CMOS/TTL data (18 bits of RGB and 3 bits of Hsync, Vsync and DE). Both Receivers' outputs are Falling edge strobe. A Rising edge or Falling edge strobe transmitter (DS90C383A/DS90C363A) will interoperate with a Falling edge strobe Receiver without any translation logic.
The DS90CF384A / DS90CF364A devices are enhanced over prior generation receivers and provided a wider data valid time on the receiver output.
This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.
技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | DS90CF384A/364A 3.3V LVDS Rcvr 24Bit FPD Link 65MHz/18Bit FPD Link - 65 MHz datasheet (Rev. I) | 2013年 4月 19日 | |
Application note | How to Map RGB Signals to LVDS/OpenLDI(OLDI) Displays (Rev. A) | 2018年 6月 29日 | ||
Application note | AN-1032 An Introduction to FPD-Link (Rev. C) | 2017年 8月 8日 | ||
Application note | Receiver Skew Margin for Channel Link I and FPD Link I Devices | 2016年 1月 13日 | ||
Application note | TFT Data Mapping for Dual Pixel LDI Application - Alternate A - Color Map | 2004年 5月 15日 | ||
Application note | AN-1056 STN Application Using FPD-Link | 2004年 5月 14日 | ||
Application note | AN-1085 FPD-Link PCB and Interconnect Design-In Guidelines | 2004年 5月 14日 |
設計與開發
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The FPD-Link evaluation kit includes a transmitter (Tx) board, a receiver (Rx) board and interfacing cables. This kit shows the chipsets interfacing from test equipment or a graphics controller using low-voltage differential signaling (LVDS) to a receiver board.
The transmitter board accepts (...)
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
TINA-TI — 基於 SPICE 的類比模擬程式
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
TSSOP (DGG) | 56 | Ultra Librarian |
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