DS90CP22
- DC - 800 Mbps Low Jitter, Low Skew Operation
- 65 ps (typ) of Pk-Pk Jitter with PRBS = 223−1 Data Pattern at 800 Mbps
- Single +3.3 V Supply
- Less than 330 mW (typ) Total Power Dissipation
- Non-Blocking "'Switch Architecture"'
- Balanced Output Impedance
- Output Channel-to-Channel Skew is 35 ps (typ)
- Configurable as 2:1 mux, 1:2 demux, Repeater or 1:2 Signal Splitter
- LVDS Receiver Inputs Accept LVPECL Signals
- Fast Switch Time of 1.2ns (typ)
- Fast Propagation Delay of 1.3ns (typ)
- Receiver Input Threshold < ±100 mV
- Available in 16 Lead TSSOP and SOIC Packages
- Conforms to ANSI/TIA/EIA-644-1995 LVDS Standard
- Operating Temperature: −40°C to +85°C
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DS90CP22 is a 2x2 crosspoint switch utilizing LVDS (Low Voltage Differential Signaling) technology for low power, high speed operation. Data paths are fully differential from input to output for low noise generation and low pulse width distortion. The non-blocking design allows connection of any input to any output or outputs. LVDS I/O enable high speed data transmission for point-to-point interconnects. This device can be used as a high speed differential crosspoint, 2:1 mux, 1:2 demux, repeater or 1:2 signal splitter. The mux and demux functions are useful for switching between primary and backup circuits in fault tolerant systems. The 1:2 signal splitter and 2:1 mux functions are useful for distribution of serial bus across several rack-mounted backplanes.
The DS90CP22 accepts LVDS signal levels, LVPECL levels directly or PECL with attenuation networks.
The individual LVDS outputs can be put into TRI-STATE by use of the enable pins.
For more details, please refer to the section of this datasheet.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | DS90CP22 800 Mbps 2x2 LVDS Crosspoint Switch datasheet (Rev. E) | 2013年 4月 22日 | |
| White paper | LVDS, CML, ECL-differential interfaces with odd voltages | 2003年 5月 1日 | ||
| White paper | Digital Microphones - Applications and System Partitioning | 2003年 4月 1日 | ||
| White paper | Making the Most of Your LVDS - 5 Tips for Buffering Signal Integrity Headaches | 2001年 8月 1日 |
設計與開發
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PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
TINA-TI — 基於 SPICE 的類比模擬程式
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SOIC (D) | 16 | Ultra Librarian |
| TSSOP (PW) | 16 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。