SCAN926260
- Deserializes One to Six Bus LVDS Input Serial Data Streams with Embedded Clocks
- IEEE 1149.1 (JTAG) Compliant and At-Speed BIST Test Modes
- Parallel Clock Rate 16-66MHz
- On Chip Filtering for PLL
- High Impedance Inputs Upon Power Off (Vcc = 0V)
- Single Power Supply at +3.3V
- 196-Pin NFBGA Package (Low-Profile Ball Grid Array) Package
- Industrial Temperature Range Operation: −40°C to +85°C
- ROUTn[0:9] and RCLKn Default High when Channel is Not Locked
- Powerdown Per Channel to Conserve Power on Unused Channels
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The SCAN926260 integrates six 10-bit deserializer devices into a single chip. The SCAN926260 can simultaneously deserialize up to six data streams that have been serialized by TI’s 10-bit Bus LVDS serializers. In addition, the SCAN926260 is compliant with IEEE standard 1149.1 and also features an At-Speed Built-In Self Test (BIST). For more details, please see the sections titled IEEE 1149.1 Test Modes and BIST Alone Test Modes.
Each deserializer block in the SCAN926260 has it’s own powerdown pin (PWRDWN[n])and operates independently with its own clock recovery circuitry and lock-detect signaling. In addition, a master powerdown pin (MS_PWRDWN) which puts all the entire device into sleep mode is provided.
The SCAN926260 uses a single +3.3V power supply and consumes 1.2W at 3.3V with a PRBS-15 pattern on all channels at 660Mbps.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | SCAN926260 Six 1-10 Bus LVDS Deserializers w/IEEE 1149.1 & At-Speed BIST datasheet (Rev. H) | 2013年 4月 17日 |
設計與開發
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PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
TINA-TI — 基於 SPICE 的類比模擬程式
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| NFBGA (NZH) | 196 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點