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HDMI、顯示介面和 MIPI IC

SN65DSI86

現行

雙通道 MIPI® DSI 至嵌入式 DisplayPort™ (eDP) 橋接器

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產品規格表

SN65DSI86

現行
產品規格表 立即訂購

產品詳細資料

Type Bridge Protocols MIPI DSI, eDP Rating Catalog Speed (max) (Gbps) 12 Supply voltage (V) 1.2 Operating temperature range (°C) -40 to 85
Type Bridge Protocols MIPI DSI, eDP Rating Catalog Speed (max) (Gbps) 12 Supply voltage (V) 1.2 Operating temperature range (°C) -40 to 85
NFBGA (ZXH) 64 25 mm² 5 x 5
  • Embedded DisplayPort™ ( eDP™) 1.4 compliant supporting 1, 2, or 4 lanes at 1.62 Gbps (RBR), 2.16 Gbps, 2.43 Gbps, 2.7 Gbps (HBR), 3.24 Gbps, 4.32 Gbps, or 5.4 Gbps (HBR2).
  • Implements MIPI D-PHY version 1.1 physical layer front-end and display serial interface (DSI) version 1.02.00
  • Dual-channel DSI receiver configurable for one, two, three, or four D-PHY data lanes per channel operating up to 1.5 Gbps per lane
  • Supports 18 bpp and 24 bpp DSI video packets with RGB666 and RGB888 formats
  • Suitable for 60 fps 4K 4096 × 2304 resolution at 18 bpp color, and WUXGA 1920 × 1200 resolution with 3D graphics at 60 fps (120 fps equivalent)
  • MIPI front-end configurable for single-channel or dual-channel DSI configuration
  • Supports dual-channel DSI odd, even and left, right operating modes
  • 1.2-V main VCC power supply and 1.8-V supply for digital I/Os
  • Low-power features include panel refresh and MIPI ultralow power state (ULPS) support
  • DisplayPort lane polarity and assignment configurable.
  • Supports 12-MHz, 19.2-MHz, 26-MHz, 27-MHz, and 38.4-MHz frequencies through external reference clock (REFCLK)
  • ESD rating ±4 kV (HBM)
  • Packaged in 64ball 5-mm x 5-mm nFBGA (ZXH)
  • I2C configurable
  • Temperature range: –40°C to +85°C
  • Embedded DisplayPort™ ( eDP™) 1.4 compliant supporting 1, 2, or 4 lanes at 1.62 Gbps (RBR), 2.16 Gbps, 2.43 Gbps, 2.7 Gbps (HBR), 3.24 Gbps, 4.32 Gbps, or 5.4 Gbps (HBR2).
  • Implements MIPI D-PHY version 1.1 physical layer front-end and display serial interface (DSI) version 1.02.00
  • Dual-channel DSI receiver configurable for one, two, three, or four D-PHY data lanes per channel operating up to 1.5 Gbps per lane
  • Supports 18 bpp and 24 bpp DSI video packets with RGB666 and RGB888 formats
  • Suitable for 60 fps 4K 4096 × 2304 resolution at 18 bpp color, and WUXGA 1920 × 1200 resolution with 3D graphics at 60 fps (120 fps equivalent)
  • MIPI front-end configurable for single-channel or dual-channel DSI configuration
  • Supports dual-channel DSI odd, even and left, right operating modes
  • 1.2-V main VCC power supply and 1.8-V supply for digital I/Os
  • Low-power features include panel refresh and MIPI ultralow power state (ULPS) support
  • DisplayPort lane polarity and assignment configurable.
  • Supports 12-MHz, 19.2-MHz, 26-MHz, 27-MHz, and 38.4-MHz frequencies through external reference clock (REFCLK)
  • ESD rating ±4 kV (HBM)
  • Packaged in 64ball 5-mm x 5-mm nFBGA (ZXH)
  • I2C configurable
  • Temperature range: –40°C to +85°C

The SN65DSI86 DSI to embedded DisplayPort (eDP) bridge features a dual-channel MIPI D-PHY receiver front-end configuration with four lanes per channel operating at 1.5 Gbps per lane and a maximum input bandwidth of 12 Gbps. The bridge decodes MIPI DSI 18-bpp RGB666 and 24-bpp RGB888 packets and converts the formatted video data stream to a DisplayPort with up to four lanes at either 1.62 Gbps, 2.16 Gbps, 2.43 Gbps, 2.7 Gbps, 3.24 Gbps, 4.32 Gbps, or 5.4 Gbps.

The SN65DSI86 is well suited for WQXGA at 60 frames per second, as well as 3D graphics at 4K and true HD (1920 × 1080) resolutions at an equivalent 120 fps with up to 24 bpp. Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and DisplayPort interfaces.

The SN65DSI86 DSI to embedded DisplayPort (eDP) bridge features a dual-channel MIPI D-PHY receiver front-end configuration with four lanes per channel operating at 1.5 Gbps per lane and a maximum input bandwidth of 12 Gbps. The bridge decodes MIPI DSI 18-bpp RGB666 and 24-bpp RGB888 packets and converts the formatted video data stream to a DisplayPort with up to four lanes at either 1.62 Gbps, 2.16 Gbps, 2.43 Gbps, 2.7 Gbps, 3.24 Gbps, 4.32 Gbps, or 5.4 Gbps.

The SN65DSI86 is well suited for WQXGA at 60 frames per second, as well as 3D graphics at 4K and true HD (1920 × 1080) resolutions at an equivalent 120 fps with up to 24 bpp. Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and DisplayPort interfaces.
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類型 標題 日期
* Data sheet SN65DSI86 MIPI DSI to eDP Bridge datasheet (Rev. C) 2020年 10月 1日
Application brief SN65DSI86 Programming Guide 2018年 8月 17日
EVM User's guide SN65DSI86/SN65DSI96 EVM User’s Manual 2014年 6月 21日
Application note SN65DSI86 and SN65DSI96 Hardware Implementation Guide 2013年 10月 8日

設計與開發

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開發板

SN65DSI86EVM — MIPI® DSI 橋接至 eDP 評估模組

The SN65DSI86EVM evaluation module (EVM) is a printed-circuit board (PCB) to help you evaluate the SN65DSI86 device for video applications with DSI and DisplayPort interface. This EVM can also be used as a hardware reference design for any implementation of the SN65DSI86.

使用指南: PDF
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IDE、配置、編譯器或偵錯程式

DSI-TUNER — 調諧器視訊配置軟體工具

DSI 調諧器視訊配置工具可產生使用 SN65DSI8x DSI 轉 LVDS 橋接裝置，傳輸 DSI 資料至 LVDS 面板所需的視訊計時和配置暫存器值。計時和暫存器值是根據工具中提供的輸入欄位中輸入的值來計算。
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模擬型號

SN65DSI86 IBIS Model

SLLM226.ZIP (92 KB) - IBIS Model
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模擬型號

SN65DSI86 IBIS Model (Rev. A)

SLLM226A.ZIP (92 KB) - IBIS Model
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模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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TINA-TI — 基於 SPICE 的類比模擬程式

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
使用指南: PDF
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