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SN65EL11

現行

PECL/ECL 1:2 扇出緩衝器

產品詳細資料

Rating Catalog Operating temperature range (°C) -40 to 85
Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 8 29.4 mm² 4.9 x 6 VSSOP (DGK) 8 14.7 mm² 3 x 4.9
  • 1:2 PECL/ECL Fanout Buffer
  • Operating Range
    • PECL: VCC = 4.2 V to 5.7 V With VEE = 0 V
    • NECL: VCC = 0 V With VEE = -4.2 V to -5.7 V
  • 5-ps Skew Between Outputs
  • Support for Clock Frequencies >2.5 GHz
  • 265-ps Typical Propagation Delay
  • Deterministic Output Value for Open Input Conditions
  • Drop-In Compatible With MC10EL11, MC100EL11
  • Built-In Input Pulldown Resistors
  • Built-In Temperature Compensation
  • APPLICATIONS
    • Data and Clock Transmission Over Backplane
    • Signaling Level Conversion
  • 1:2 PECL/ECL Fanout Buffer
  • Operating Range
    • PECL: VCC = 4.2 V to 5.7 V With VEE = 0 V
    • NECL: VCC = 0 V With VEE = -4.2 V to -5.7 V
  • 5-ps Skew Between Outputs
  • Support for Clock Frequencies >2.5 GHz
  • 265-ps Typical Propagation Delay
  • Deterministic Output Value for Open Input Conditions
  • Drop-In Compatible With MC10EL11, MC100EL11
  • Built-In Input Pulldown Resistors
  • Built-In Temperature Compensation
  • APPLICATIONS
    • Data and Clock Transmission Over Backplane
    • Signaling Level Conversion

The SN65EL11 is a differential 1:2 PECL/ECL fanout buffer. The device includes circuitry to maintain a known logic level when inputs are in an open condition. The SN65EL11 is housed in an industry-standard SOIC-8 package and is also available in a TSSOP-8 package.

The SN65EL11 is a differential 1:2 PECL/ECL fanout buffer. The device includes circuitry to maintain a known logic level when inputs are in an open condition. The SN65EL11 is housed in an industry-standard SOIC-8 package and is also available in a TSSOP-8 package.

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技術文件

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類型 標題 日期
* Data sheet 5-V PECL/ECL 1:2 Fanout Buffer datasheet 2008年 11月 26日
Application note AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C) 2007年 10月 17日

設計與開發

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模擬型號

SN65EL11 IBIS Model Version 1.1

SLLM048.ZIP (15 KB) - IBIS Model
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PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
使用指南: PDF
封裝 引腳 下載
SOIC (D) 8 檢視選項
VSSOP (DGK) 8 檢視選項

訂購與品質

內含資訊:
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 資格摘要
  • 進行中可靠性監測
內含資訊:
  • 晶圓廠位置
  • 組裝地點

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