SN65LVDS104
- Receiver and Drivers Meet or Exceed the
Requirements of ANSI EIA/TIA-644 Standard- SN65LVDS105 Receives Low-Voltage TTL
(LVTTL) Levels - SN65LVDS104 Receives Differential Input
Levels, ±100 mV
- SN65LVDS105 Receives Low-Voltage TTL
- Typical Data Signaling Rates to 400 Mbps or
Clock Frequencies to 400 MHz - Operates From a Single 3.3-V Supply
- Low-Voltage Differential Signaling With Typical
Output Voltage of 350 mV and a 100-Ω Load - Propagation Delay Time
- SN65LVDS105 – 2.2 ns (Typ)
- SN65LVDS104 – 3.1 ns (Typ)
- LVTTL Levels Are 5-V Tolerant
- Electrically Compatible With LVDS, PECL,
LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT,
SSTL, or HSTL Outputs With External Networks - Driver Outputs Are High-Impedance When
Disabled or With VCC <1.5 V - Bus-Pin ESD Protection Exceeds 16 kV
- SOIC and TSSOP Packaging
The SN65LVDS10x are a differential line receiver and a LVTTL input (respectively) connected to four differential line drivers that implement the electrical characteristics of low-voltage differential signaling (LVDS). LVDS, as specified in EIA/TIA-644 is a data signaling technique that offers low-power, low-noise coupling, and switching speeds to transmit data at relatively long distances. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.)
The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables. Having the drivers integrated into the same substrate, along with the low pulse skew of balanced signaling, allows extremely precise timing alignment of the signals repeated from the input. This is particularly advantageous in distribution or expansion of signals such as clock or serial data stream.
The SN65LVDS10x are characterized for operation from –40°C to 85°C.
The SN65LVDS10x are members of a family of LVDS repeaters. A brief overview of the family is provided in the Selection Guide to LVDS Repeaters section.
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技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | SN65LVDS10x 4-Port LVDS and 4-Port TTL-to-LVDS Repeaters datasheet (Rev. G) | PDF | HTML | 2015/12/31 | ||
| 應用說明 | AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C) | 2007/10/17 | ||||
| 應用說明 | DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CML | 2003/2/19 |
設計與開發
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| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SOIC (D) | 16 | Ultra Librarian |
| TSSOP (PW) | 16 | Ultra Librarian |
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