SN65MLVD047

現行

多點 LVDS 四路差動線路驅動器

產品詳細資料

Function Driver Protocols M-LVDS Number of transmitters 4 Number of receivers 0 Supply voltage (V) 3.3 Signaling rate (MBits) 200 Input signal LVTTL Output signal M-LVDS Rating Catalog Operating temperature range (°C) -40 to 85
Function Driver Protocols M-LVDS Number of transmitters 4 Number of receivers 0 Supply voltage (V) 3.3 Signaling rate (MBits) 200 Input signal LVTTL Output signal M-LVDS Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 16 59.4 mm² 9.9 x 6 TSSOP (PW) 16 32 mm² 5 x 6.4
  • Differential Line Drivers for 30- Loads and Data Rates(1) Up to 200 Mbps, Clock Frequencies up to 100 MHz
  • Supports Multipoint Bus Architectures
  • Operates from a Single 3.3-V Supply
  • Characterized for Operation from -40°C to 85°C
  • 16-Pin SOIC (JEDEC MS-012) and 16-Pin TSSOP (JEDEC MS-153) Packaging
  • APPLICATIONS
    • Clock Distribution
    • Backplane or Cabled Multipoint Data Transmission in Telecommunications, Automotive, Industrial, and Other Computer Systems
    • Cellular Base Stations
    • Central-Office and PBX Switching
    • Bridges and Routers
    • Low-Power High-Speed Short-Reach Alternative to TIA/EIA-485

(1) The data rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).

  • Differential Line Drivers for 30- Loads and Data Rates(1) Up to 200 Mbps, Clock Frequencies up to 100 MHz
  • Supports Multipoint Bus Architectures
  • Operates from a Single 3.3-V Supply
  • Characterized for Operation from -40°C to 85°C
  • 16-Pin SOIC (JEDEC MS-012) and 16-Pin TSSOP (JEDEC MS-153) Packaging
  • APPLICATIONS
    • Clock Distribution
    • Backplane or Cabled Multipoint Data Transmission in Telecommunications, Automotive, Industrial, and Other Computer Systems
    • Cellular Base Stations
    • Central-Office and PBX Switching
    • Bridges and Routers
    • Low-Power High-Speed Short-Reach Alternative to TIA/EIA-485

(1) The data rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).

The SN65MLVD047 is a quadruple line driver. The output current of this device has been increased, in comparison to standard LVDS compliant devices, in order to support doubly terminated transmission lines and heavily loaded backplane bus applications. Backplane applications generally require impedance matching termination resistors at both ends of the bus. The effective impedance of a doubly terminated bus can be as low as 30 . The SN65MLVD047 devices allow for multiple drivers to be present on a single bus. Driver edge rate control is incorporated to support operation. The SN65MLVD047 provides 9-kV ESD protection on all bus pins.

The SN65MLVD047 is a quadruple line driver. The output current of this device has been increased, in comparison to standard LVDS compliant devices, in order to support doubly terminated transmission lines and heavily loaded backplane bus applications. Backplane applications generally require impedance matching termination resistors at both ends of the bus. The effective impedance of a doubly terminated bus can be as low as 30 . The SN65MLVD047 devices allow for multiple drivers to be present on a single bus. Driver edge rate control is incorporated to support operation. The SN65MLVD047 provides 9-kV ESD protection on all bus pins.

下載 觀看有字幕稿的影片 影片

技術文件

star =TI 所選的此產品重要文件
找不到結果。請清除您的搜尋條件,然後再試一次。
檢視所有 1
類型 標題 日期
* Data sheet Multipoint-LVDS Quad Differential Line Driver datasheet (Rev. A) 2005年 7月 12日

設計與開發

如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。

模擬型號

SN65MLVD047 IBIS Model

SLLC208.ZIP (9 KB) - IBIS Model
模擬型號

SN65MLVD047DW IBIS Model

SLLC209.ZIP (9 KB) - IBIS Model
模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
模擬工具

TINA-TI — 基於 SPICE 的類比模擬程式

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
使用指南: PDF
封裝 引腳 下載
SOIC (D) 16 檢視選項
TSSOP (PW) 16 檢視選項

訂購與品質

內含資訊:
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 資格摘要
  • 進行中可靠性監測
內含資訊:
  • 晶圓廠位置
  • 組裝地點

建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

內容係由 TI 和社群貢獻者依「現狀」提供,且不構成 TI 規範。檢視使用條款

若有關於品質、封裝或訂購 TI 產品的問題,請參閱 TI 支援。​​​​​​​​​​​​​​

影片