首頁 介面 乙太網路 IC 乙太網路重定時器、訊號調節器和多工器緩衝器
首頁
介面
乙太網路 IC
乙太網路重定時器、訊號調節器和多工器緩衝器

TLK1002A

現行

1.0 至 1.3-Gbps 雙訊號調節收發器

立即訂購
產品規格表

TLK1002A

現行
產品規格表 立即訂購

產品詳細資料

Type Retimer Number of channels 2 Speed (max) (Gbpp) 1.3 Input compatibility CMOS Protocols Telecom SerDes Operating temperature range (°C) 0 to 70
Type Retimer Number of channels 2 Speed (max) (Gbpp) 1.3 Input compatibility CMOS Protocols Telecom SerDes Operating temperature range (°C) 0 to 70
VQFN (RGE) 24 16 mm² 4 x 4
  • Fully Integrated Signal Conditioning
    Transceiver
  • 1.0-1.3 Gbps Operation
  • Low Power CMOS Design (<300 mW)
  • High Differential Output Voltage Swing (1600 mVp-p typical)
  • 400 mVp-p Differential Input Sensitivity
  • High Input Jitter Tolerance 0.606 UI
  • Single 1.8 V Power Supply
  • 2.5 V Tolerant Control Inputs
  • Differential VML Transmit Outputs With No External Components Necessary
  • No External Filter Components Required for PLLs
  • Supports Loop-Back Modes
  • Temperature Rating 0°C to 70°C
  • Small Footprint 4 mm × 4 mm 24-Lead QFN Package
  • APPLICATIONS
    • Resynchronization in Both Directions for 1.25 Gbps Links
    • Repeater for 1.0625 Gbps Applications
  • Fully Integrated Signal Conditioning
    Transceiver
  • 1.0-1.3 Gbps Operation
  • Low Power CMOS Design (<300 mW)
  • High Differential Output Voltage Swing (1600 mVp-p typical)
  • 400 mVp-p Differential Input Sensitivity
  • High Input Jitter Tolerance 0.606 UI
  • Single 1.8 V Power Supply
  • 2.5 V Tolerant Control Inputs
  • Differential VML Transmit Outputs With No External Components Necessary
  • No External Filter Components Required for PLLs
  • Supports Loop-Back Modes
  • Temperature Rating 0°C to 70°C
  • Small Footprint 4 mm × 4 mm 24-Lead QFN Package
  • APPLICATIONS
    • Resynchronization in Both Directions for 1.25 Gbps Links
    • Repeater for 1.0625 Gbps Applications

TLK1002A is a single-chip dual signal conditioning transceiver.

This chip supports data rates from 1.0 Gbps up to 1.3 Gbps. An on-chip clock generation phase-locked loop (PLL) generates the required half-rate clock from an externally applied reference clock. This reference clock equals approximately one tenth of the data rate. It may be off frequency from both received data streams by up to ±200 ppm.

Both data paths are implemented identical. The implemented input buffers provide an input sensitivity of 400 mVp-p differential.

The data paths tolerate up to 0.606 UI total input jitter. Signal retiming is performed by means of phase-locked loop (PLL) circuits. The retimed output signals are fed to VML output buffers, which provide output amplitudes of typical 1600mVp-p differential across the external 2x50 load.

TLK1002A only requires a single 1.8 V supply voltage. Robust design avoids the necessity of special off-chip supply filtering.

Advanced low power CMOS design leads to low power consumption.

TLK1002A is a single-chip dual signal conditioning transceiver.

This chip supports data rates from 1.0 Gbps up to 1.3 Gbps. An on-chip clock generation phase-locked loop (PLL) generates the required half-rate clock from an externally applied reference clock. This reference clock equals approximately one tenth of the data rate. It may be off frequency from both received data streams by up to ±200 ppm.

Both data paths are implemented identical. The implemented input buffers provide an input sensitivity of 400 mVp-p differential.

The data paths tolerate up to 0.606 UI total input jitter. Signal retiming is performed by means of phase-locked loop (PLL) circuits. The retimed output signals are fed to VML output buffers, which provide output amplitudes of typical 1600mVp-p differential across the external 2x50 load.

TLK1002A only requires a single 1.8 V supply voltage. Robust design avoids the necessity of special off-chip supply filtering.

Advanced low power CMOS design leads to low power consumption.
filter 尋找其它 乙太網路重定時器、訊號調節器和多工器緩衝器
下載 觀看有字幕稿的影片 影片

技術文件

star =TI 所選的此產品重要文件
找不到結果。請清除您的搜尋條件，然後再試一次。
檢視所有 1
重要文件 類型 標題 格式選項 日期
* Data sheet Dual Signal Conditioning Transceiver datasheet 2005年 6月 28日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI 是有助於評估類比電路功能的設計和模擬環境。這款全功能設計和模擬套件使用 Cadence® 的類比分析引擎。PSpice for TI 包括業界最大的模型庫之一，涵蓋我們的類比和電源產品組合，以及特定類比行為模型，且使用無需支付費用。

PSpice for TI 設計和模擬環境可讓您使用其內建函式庫來模擬複雜的混合訊號設計。在進行佈局和製造之前，建立完整的終端設備設計和解決方案原型，進而縮短上市時間並降低開發成本。 

在 PSpice for TI 設計與模擬工具中，您可以搜尋 TI (...)
要求
模擬工具

TINA-TI — 基於 SPICE 的類比模擬程式

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
使用指南: PDF
View Options
封裝 針腳 CAD 符號、佔位空間與 3D 模型
VQFN (RGE) 24 Ultra Librarian
適用 TI 的評估品項標準條款與條件。

訂購與品質

內含資訊：
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中的可靠性監測
內含資訊：
  • 晶圓廠位置
  • 組裝地點

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

以英文檢視所有論壇主題

內容係由 TI 和社群貢獻者依「現狀」提供，且不構成 TI 規範。檢視使用條款。

若有關於品質、封裝或訂購 TI 產品的問題，請參閱 TI 支援。​​​​​​​​​​​​​​

影片