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乙太網路 IC
乙太網路重定時器、訊號調節器和多工器緩衝器

TLK1002A

現行

1.0 至 1.3-Gbps 雙訊號調節收發器

立即訂購
產品規格表

TLK1002A

現行
產品規格表 立即訂購

產品詳細資料

Type Retimer Number of channels 2 Input compatibility CMOS Speed (max) (Gbps) 1.3 Protocols Telecom SerDes Operating temperature range (°C) 0 to 70
Type Retimer Number of channels 2 Input compatibility CMOS Speed (max) (Gbps) 1.3 Protocols Telecom SerDes Operating temperature range (°C) 0 to 70
VQFN (RGE) 24 16 mm² 4 x 4
  • Fully Integrated Signal Conditioning
    Transceiver
  • 1.0-1.3 Gbps Operation
  • Low Power CMOS Design (<300 mW)
  • High Differential Output Voltage Swing (1600 mVp-p typical)
  • 400 mVp-p Differential Input Sensitivity
  • High Input Jitter Tolerance 0.606 UI
  • Single 1.8 V Power Supply
  • 2.5 V Tolerant Control Inputs
  • Differential VML Transmit Outputs With No External Components Necessary
  • No External Filter Components Required for PLLs
  • Supports Loop-Back Modes
  • Temperature Rating 0°C to 70°C
  • Small Footprint 4 mm × 4 mm 24-Lead QFN Package
  • APPLICATIONS
    • Resynchronization in Both Directions for 1.25 Gbps Links
    • Repeater for 1.0625 Gbps Applications
  • Fully Integrated Signal Conditioning
    Transceiver
  • 1.0-1.3 Gbps Operation
  • Low Power CMOS Design (<300 mW)
  • High Differential Output Voltage Swing (1600 mVp-p typical)
  • 400 mVp-p Differential Input Sensitivity
  • High Input Jitter Tolerance 0.606 UI
  • Single 1.8 V Power Supply
  • 2.5 V Tolerant Control Inputs
  • Differential VML Transmit Outputs With No External Components Necessary
  • No External Filter Components Required for PLLs
  • Supports Loop-Back Modes
  • Temperature Rating 0°C to 70°C
  • Small Footprint 4 mm × 4 mm 24-Lead QFN Package
  • APPLICATIONS
    • Resynchronization in Both Directions for 1.25 Gbps Links
    • Repeater for 1.0625 Gbps Applications

TLK1002A is a single-chip dual signal conditioning transceiver.

This chip supports data rates from 1.0 Gbps up to 1.3 Gbps. An on-chip clock generation phase-locked loop (PLL) generates the required half-rate clock from an externally applied reference clock. This reference clock equals approximately one tenth of the data rate. It may be off frequency from both received data streams by up to ±200 ppm.

Both data paths are implemented identical. The implemented input buffers provide an input sensitivity of 400 mVp-p differential.

The data paths tolerate up to 0.606 UI total input jitter. Signal retiming is performed by means of phase-locked loop (PLL) circuits. The retimed output signals are fed to VML output buffers, which provide output amplitudes of typical 1600mVp-p differential across the external 2x50 load.

TLK1002A only requires a single 1.8 V supply voltage. Robust design avoids the necessity of special off-chip supply filtering.

Advanced low power CMOS design leads to low power consumption.

TLK1002A is a single-chip dual signal conditioning transceiver.

This chip supports data rates from 1.0 Gbps up to 1.3 Gbps. An on-chip clock generation phase-locked loop (PLL) generates the required half-rate clock from an externally applied reference clock. This reference clock equals approximately one tenth of the data rate. It may be off frequency from both received data streams by up to ±200 ppm.

Both data paths are implemented identical. The implemented input buffers provide an input sensitivity of 400 mVp-p differential.

The data paths tolerate up to 0.606 UI total input jitter. Signal retiming is performed by means of phase-locked loop (PLL) circuits. The retimed output signals are fed to VML output buffers, which provide output amplitudes of typical 1600mVp-p differential across the external 2x50 load.

TLK1002A only requires a single 1.8 V supply voltage. Robust design avoids the necessity of special off-chip supply filtering.

Advanced low power CMOS design leads to low power consumption.
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* Data sheet Dual Signal Conditioning Transceiver datasheet 2005年 6月 28日

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