SLUSDF9 June 2020 BQ25790
After the REGN LDO powers up, the device checks the current capability of the input source. The input source has to meet the following requirements in order to move forward to the next power on steps.
Once the conditions are met, the status register bit PG_STAT is set high and the INT pin is pulsed to signal the host. The PG pin goes LOW.
If VBUS_OVP is detected (condition 1 above), the device automatically retries detection once the over-voltage fault goes away. If a poor source is detected (when pulling IPOORSRC, the VBUS voltage drops below VPOORSRC), the device repeats poor source qualification routine every 2 seconds. After 7 consecutive failures, the device sets EN_HIZ = 1 and goes to HIZ mode. The battery must have enough charge to power the system while the device is in HIZ. Adapter re-plugin or EN_HIZ bit toggle is required when the input source can be used to power the device. The EN_HIZ bit is cleared automatically when the adapter is plugged in. Whenever the VBUS voltage does not meet either condition 1 or condition 2, it means the input source is not qualified anymore, the PG pin goes HIGH and the PG_STAT bit goes low, at the same time, an INT pulse will be asserted and PG_FLAG will be set to 1, if PG_MASK = 0.