SCAS928D Data sheet

SCAS928D May 2012 – April 2019 CDCUN1208LP

PRODUCTION DATA.

Package Options

Mechanical Data (Package|Pins)

RHB|32
- MPQF130D

Thermal pad, mechanical data (Package|Pins)

RHB|32
- QFND029X

Orderable Information

6.8 Clock Output Buffer Characteristics (Output Mode = HCSL)

Unless otherwise noted, V_DDOx = 1.8 V, 2.5 V, 3.3 V; T_A = –40°C to 85°C. See Figure 18, Figure 19, and Figure 20.
Supporting PCIe Gen1, Gen2, Gen3.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
f_OUT	Output frequency		0.008		400	MHz
Vmax	Absolute maximum output voltage⁽¹⁾	See Figure 1			1.15	V
Vmin	Absolute minimum output voltage⁽²⁾	See Figure 1	–0.3			V
V_OH	Single-ended output voltage – high⁽³⁾	R_L= single ended to GND = 50 Ω, C_L = 2 pF, VDDOx = 2.5 V, 3.3 V See Figure 18	600			mV
V_OH	Single-ended output voltage – high⁽³⁾	R_L= single ended to GND = 50 Ω, C_L = 2 pF, VDDOx = 1.8 V See Figure 18	550			mV
V_OL	Single-ended output voltage – low⁽³⁾	R_L = single ended to GND = 50 Ω, C_L = 2 pF, See Figure 18			150	mV
V_CROSS	Output crossing point voltage⁽³⁾	See Figure 1	250		550	mV
V_CROSSΔ	V_CROSS Total variation⁽³⁾	See Figure 2			140	mV
V_RB	Ring back voltage margin⁽³⁾	See Figure 3	–100		100	mV
T_STABLE	Time before V_RB is Allowed⁽³⁾,⁽⁴⁾	See Figure 3	500			ps
V_OS	Output AC common mode	V_{IN, DIFF, PP} = 0.9 V, R_L = single ended to GND = 50 Ω, 2 pF		75	125	mV_P-P
T_jitHCSL	Additive jitter, input set to HCSL⁽⁵⁾	f_OUT = 100 MHz, 10k-20M integration bandwidth. Differential measurement			380	fs, rms
T_jitLVDS	Additive jitter, input set to LVDS⁽⁵⁾	f_OUT = 100 MHz, 10k-20M integration bandwidth. Differential measurement			280	fs, rms
t_R/t_F	Output rise/fall time⁽⁶⁾	Slow, +150-mV differential, see Figure 4, V_DDOx = 3.3 V		300		ps
		Slow, +150-mV differential, see Figure 4, V_DDOx = 1.8 V		230
		Med., +150-mV differential, see Figure 4, V_DDOx = 3.3 V		240
		Med., +150-mV differential, see Figure 4, V_DDOx = 1.8 V		180
		Fast, +150-mV differential, see Figure 4		140
TM_RF	Output rise/fall time matching	See Figure 5			20%
ODC	Output duty cycle⁽⁷⁾	Differential measurement, see Figure 6	45%		55%
T_DLYO	Propagation delay	ERC set to high rate. Input t_r, t_f> 0.6 V/ns, V_DD = 2.5 V, 3.3 V			3.8	ns
T_DLYO	Propagation delay	ERC set to high rate. Input t_r, t_f > 0.6 V/ns, V_DD = 1.8 V			4.3	ns
t_SKEW	Skew between outputs⁽⁸⁾	Differential Measurement, Input t_r, t_f> 0.6 V/ns		35	50	ps
t_OE	Output enable to stable clock output	Pin mode, f_out = 100 MHz, device in active mode with outputs disabled, OE asserted		2		µs
t_PD	PD de-asserted to stable clock output	Host mode, f_out= 100 MHz, device in power down mode, PD de-asserted		15		µs
t_PU	Time from power applied to stable clock output⁽⁹⁾	Pin mode, f_out= 100 MHz, OE asserted, measured from time V_DD is valid to stable output		1		ms

(1) Single-ended measurement includes overshoot. Measurement is taken at load capacitors C_L (see Figure 18).

(2) Single-ended measurement, includes undershoot. Measurement is taken at load capacitors C_L (see Figure 18).

(3) Measurement is taken at load capacitors C_L (see Figure 18). If VDDOx = 1.8 V, the specified minimum V_OH is 550 mV.

(4) TSTABLE is the time the differential clock must maintain a minimum ±150 mV differential voltage after rising/falling edges, before it is allowed to return into the VRB ±100 mV differential range. See Figure 3.

(5) t_Rfin = t_Ffin ≥ 0.6 V/ns.

(6) Measured from –150 mV to +150 mV on the differential waveform. The signal must be monotonic through the measurement region for rise and fall time. The 300-mV measurement window is centered on the differential zero crossing. Slow is 0.53 V/ns, medium is 1.05 V/ns, and fast is 2.1 V/ns. The PCIe CEM spec. has a window of 0.6 V/ns to 4 V/ns.

(7) Assumes input duty cycle = 50%.

(8) Skew measured between identical output types with identical loads, identical output power supplies, and identical edge rate settings.

(9) Parameter depends significantly on power supply design and supply voltage rise time.