SCAS928D May 2012 – April 2019 CDCUN1208LP
PRODUCTION DATA.
The smart multiplexer supports manual and automatic switching between IN1 and IN2. If enabled, the smart multiplexer switches automatically between clock inputs based on a prioritization scheme shown in Table 7. If using the smart multiplexer auto mode, the frequencies of the clocks applied to the smart multiplexer through IN1 and IN2 (through the divider) may differ by up to 20%. The phase relationship between clock inputs has no restrictions. The smart multiplexer includes signal conditioning that provides glitch suppression.(1)
Upon the detection of a loss of signal on the input with higher priority, the smart multiplexer switches over to the other clock input on the first incoming rising edge. During this switching operation, the output of the smart multiplexer is low. Upon restoration of the higher priority clock, the smart multiplexer waits until it detects four complete cycles from the higher priority clock prior to switching the output of the smart multiplexer back to the higher priority clock. During this switching operation, the output of the smart multiplexer remains high until the next falling edge as shown in Figure 29.