SCAS928D May   2012  – April 2019 CDCUN1208LP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Pin Configuration Overview
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Digital Input Electrical Characteristics – OE (SCL), INSEL, ITTP, OTTP, Divide (SDA/MOSI), ERC(ADDR/CS), Mode
    6. 6.6  Universal Input (IN1, IN2) Characteristics
    7. 6.7  Clock Output Buffer Characteristics (Output Mode = LVDS)
    8. 6.8  Clock Output Buffer Characteristics (Output Mode = HCSL)
    9. 6.9  Clock Output Buffer Electrical Characteristics (Output Mode = LVCMOS)
    10. 6.10 Clock Output Buffer Electrical Characteristics (Output Mode = LVCMOS) (Continued)
    11. 6.11 Clock Output Buffer Electrical Characteristics (Output Mode = LVCMOS) (Continued)
    12. 6.12 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Test Configurations
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Device Control Using Configuration Pins
        1. 8.3.1.1 Configuration of Output Type (OTTP)
        2. 8.3.1.2 Configuration of Edge Rate Control (ERC)
        3. 8.3.1.3 Control of Output Enable (OE)
      2. 8.3.2 Input Ports (IN1, IN2)
        1. 8.3.2.1 Configuration of the Input Type (ITTP)
        2. 8.3.2.2 Configuration of the IN2 Divider (INDIV)
      3. 8.3.3 Smart Input Multiplexer (INMUX)
        1. 8.3.3.1 Pin Configuration of the Smart Input Multiplexer (INMUX)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Control Using the Host Interface
        1. 8.4.1.1 OE and INSEL in Host Configuration Mode
    5. 8.5 Programming
      1. 8.5.1 Host Interface Hardware Information
        1. 8.5.1.1 SPI Communication
          1. 8.5.1.1.1 CDCUN1208LP SPI Addressing
          2. 8.5.1.1.2 Writing to the CDCUN1208LP
          3. 8.5.1.1.3 Reading From the CDCUN1208LP
          4. 8.5.1.1.4 Block Write/Read Operation
        2. 8.5.1.2 I2C Communication
          1. 8.5.1.2.1 Message Transmission
            1. 8.5.1.2.1.1 Data and Address Bits
            2. 8.5.1.2.1.2 Special Symbols – Start (S) and Stop (P)
            3. 8.5.1.2.1.3 Special Symbols – Acknowledge (ACK)
            4. 8.5.1.2.1.4 Generic Message Frame
            5. 8.5.1.2.1.5 CDCUN1208LP Message Format
            6. 8.5.1.2.1.6 CDCUN1208LP Device Addressing (I2C Address)
            7. 8.5.1.2.1.7 CDCUN1208LP Device Addressing (Register Address)
          2. 8.5.1.2.2 I2C Master and Slave Handshaking
          3. 8.5.1.2.3 Block Read/Write
          4. 8.5.1.2.4 I2C Timing
    6. 8.6 Register Maps
      1. 8.6.1 Device Registers
        1. 8.6.1.1 Device Registers: Register 00-07
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 PCI Express Applications
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
    3. 9.3 Systems Examples
  10. 10Power Supply Recommendations
    1. 10.1 CDCUN1208LP Power Consumption
    2. 10.2 Device Power Supply Connections and Sequencing
    3. 10.3 Device Inputs (IN1, IN2)
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.7 Clock Output Buffer Characteristics (Output Mode = LVDS)

Unless otherwise noted, VDDOX = 1.8 V, 2.5 V, 3.3 V; TA = –40°C to 85°C. See Figure 15, Figure 16, and Figure 17.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fOUT Output frequency 0.008 400 MHz
VCM Output common mode voltage,
VDDOx = 2.5/3.3 V		 RL = 100 Ω 1.125 1.2 1.275 V
Output common mode voltage,
VDDOx = 1.8 V		 RL = 100 Ω 0.9 V
|VOD| Differential output voltage RL = 100 Ω, single-ended Pk-Pk 250 400 550 mV
ΔVOD Change in magnitude of VOD for complementary output states RL = 100 Ω –50 50 mV
Vring Output overshoot and undershoot Percentage of output amplitude VOD 20%
VOS Output AC common mode VIN, DIFF, PP = 0.9 V, RL = 100 Ω, 2 pF 150 mVP-P
TADDJIT Additive jitter(1) fout = 100 MHz, 10k-20M integration bandwidth,
RL = 100 Ω		 200 fs, rms
fout = 400 MHz, 10k-20M integration bandwidth,
RL = 100 Ω		 180
tR/tF Output rise/fall time ERC = Slow, 20% to 80%, ZL = 100 Ω, 1pF,
VDDOx = 3.3 V		 800 ps
ERC = Slow, 20% to 80%, ZL = 100 Ω, 1pF,
VDDOx = 1.8 V		 700
ERC = Medium., 20% to 80%, ZL = 100 Ω, 1pF,
VDDOx = 3.3 V		 600
ERC = Medium., 20% to 80%, ZL = 100 Ω, 1pF,
VDDOx = 1.8 V		 500
ERC = Fast, 20% to 80%, Z L = 100 Ω, 1 pF 300
ODC Output duty cycle 50/50 Input duty cycle 45% 55%
ISP
ISN 		Output short circuit current (single ended) Shorted to GND –24 24 mA
|IPN| Output short circuit current (differential) Complementary outputs shorted together 12 mA
TDLYO Propagation delay ERC set to high rate. Input tr, tf > 0.6 V/ns, RL = 100 Ω, VDD = 2.5 V, 3.3 V 3.3 ns
ERC set to high rate. Input tr, tf > 0.6 V/ns, RL = 100 Ω, VDD = 1.8 V 3.8
tSKEW Skew between outputs ERC set to high rate. Input tr, tf > 0.6 V/ns, Equal VDDOx,
RL = 100 Ω		 35 50 ps
tOE Output enable to stable clock output Pin mode. fout = 100 MHz, device in active mode with outputs disabled, OE asserted 20 µs
tPD PD de-asserted to stable clock output Host mode, fout = 100 MHz, device in power down mode, PD de-asserted 20 µs
tPU Time from power applied to stable clock output(2) Pin mode, fout = 100 MHz, OE asserted, measured from time VDD is valid to stable output. 1 ms
(1) tRfin = tFfin > 0.6 V/ns.
(2) Parameter depends significantly on power supply design and supply voltage rise time.