SCAS928D May 2012 – April 2019 CDCUN1208LP
PRODUCTION DATA.
The CDCUN1208LP incorporates an I2C port compliant with I2C Bus Specification V2.1 (7-bit addressing). Some highlights are contained herein to provide clarity with respect to how communication between the host and the CDCUN1208LP is facilitated. The I2C bus comprises two signals (clock – SCL, and data – SDA). I2C implements a master-slave protocol and supports multi-master implementations. Unlike SPI that implements a chip select signal for device-level addressing and separate data signals for transmit and receive, I2C embeds the device address in the serial data stream. Because of this, devices that reside on the I2C must have a unique bus address. I2C also uses the protocol to control the direction of data flow through the data signaling line.