SCAS928D May   2012  – April 2019 CDCUN1208LP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Pin Configuration Overview
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Digital Input Electrical Characteristics – OE (SCL), INSEL, ITTP, OTTP, Divide (SDA/MOSI), ERC(ADDR/CS), Mode
    6. 6.6  Universal Input (IN1, IN2) Characteristics
    7. 6.7  Clock Output Buffer Characteristics (Output Mode = LVDS)
    8. 6.8  Clock Output Buffer Characteristics (Output Mode = HCSL)
    9. 6.9  Clock Output Buffer Electrical Characteristics (Output Mode = LVCMOS)
    10. 6.10 Clock Output Buffer Electrical Characteristics (Output Mode = LVCMOS) (Continued)
    11. 6.11 Clock Output Buffer Electrical Characteristics (Output Mode = LVCMOS) (Continued)
    12. 6.12 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Test Configurations
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Device Control Using Configuration Pins
        1. 8.3.1.1 Configuration of Output Type (OTTP)
        2. 8.3.1.2 Configuration of Edge Rate Control (ERC)
        3. 8.3.1.3 Control of Output Enable (OE)
      2. 8.3.2 Input Ports (IN1, IN2)
        1. 8.3.2.1 Configuration of the Input Type (ITTP)
        2. 8.3.2.2 Configuration of the IN2 Divider (INDIV)
      3. 8.3.3 Smart Input Multiplexer (INMUX)
        1. 8.3.3.1 Pin Configuration of the Smart Input Multiplexer (INMUX)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Control Using the Host Interface
        1. 8.4.1.1 OE and INSEL in Host Configuration Mode
    5. 8.5 Programming
      1. 8.5.1 Host Interface Hardware Information
        1. 8.5.1.1 SPI Communication
          1. 8.5.1.1.1 CDCUN1208LP SPI Addressing
          2. 8.5.1.1.2 Writing to the CDCUN1208LP
          3. 8.5.1.1.3 Reading From the CDCUN1208LP
          4. 8.5.1.1.4 Block Write/Read Operation
        2. 8.5.1.2 I2C Communication
          1. 8.5.1.2.1 Message Transmission
            1. 8.5.1.2.1.1 Data and Address Bits
            2. 8.5.1.2.1.2 Special Symbols – Start (S) and Stop (P)
            3. 8.5.1.2.1.3 Special Symbols – Acknowledge (ACK)
            4. 8.5.1.2.1.4 Generic Message Frame
            5. 8.5.1.2.1.5 CDCUN1208LP Message Format
            6. 8.5.1.2.1.6 CDCUN1208LP Device Addressing (I2C Address)
            7. 8.5.1.2.1.7 CDCUN1208LP Device Addressing (Register Address)
          2. 8.5.1.2.2 I2C Master and Slave Handshaking
          3. 8.5.1.2.3 Block Read/Write
          4. 8.5.1.2.4 I2C Timing
    6. 8.6 Register Maps
      1. 8.6.1 Device Registers
        1. 8.6.1.1 Device Registers: Register 00-07
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 PCI Express Applications
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
    3. 9.3 Systems Examples
  10. 10Power Supply Recommendations
    1. 10.1 CDCUN1208LP Power Consumption
    2. 10.2 Device Power Supply Connections and Sequencing
    3. 10.3 Device Inputs (IN1, IN2)
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.5.1.2.4 I2C Timing

Figure 40 and Table 10 provide details regarding the timing requirements for I2C:

CDCUN1208LP I2C_timing_dia_cas928.gifFigure 40. I2C Timing Diagram

Table 10. I2C Timing Requirements

PARAMETER MIN MAX UNIT
fSCL SCL clock frequency 0 100 kHz
tsu(START) START setup time (SCL high before SDA low) 4.7 µs
th(START) START hold time (SCL low after SDA low) 4 µs
tw(SCLL) SCL low-pulse duration 4.7 µs
tw(SCLH) SCL high-pulse duration 4 µs
th(SDA) SDA hold time (SDA valid after SCL low) 0 3.45 µs
tsu(SDA) SDA setup time 250 ns
tr SCL / SDA input rise time 1000 ns
tf SCL / SDA input fall time 300 ns
tsu(STOP) STOP setup time 4 µs
tBUS Bus free time between a STOP and START condition 4.7 µs