SCAS928D May 2012 – April 2019 CDCUN1208LP
PRODUCTION DATA.
As with the write operation, the master first initiates a SPI transfer by asserting the SCS pin low. The host signals a read operation by shifting a logical high in the first bit position, signaling the slave that the master is initiating a read data transfer from the slave. Thereafter, the master specifies the address of interest according to Figure 33. During the 16 clock cycles that follow, the slave presents the data from the register specified in the first half of the message on the SDO pin. The master signals the slave that the transfer is complete by de-asserting the SCS pin high. At no time should the clock be toggled while SCS is high. CDCUN1208LP should always be used in single-slave SPI configuration.