SLVSEA2B August   2020  – June 2021 DRV8714-Q1 , DRV8718-Q1


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1. 6.1 VQFN (RVJ) 56-Pin Package and Pin Functions
    2. 6.2 VQFN (RHA) 40-Pin Package and Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 External Components
      2. 8.3.2 Device Interface Variants
        1. Serial Peripheral Interface (SPI)
        2. Hardware (H/W)
      3. 8.3.3 Input PWM Control Modes
        1. Half-Bridge Control Scheme With Input PWM Mapping
          1. DRV8718-Q1 Half-Bridge Control
          2. DRV8714-Q1 Half-Bridge Control
        2. H-Bridge Control
          1. DRV8714-Q1 H-Bridge Control
        3. Split HS and LS Solenoid Control
          1. DRV8714-Q1 Split HS and LS Solenoid Control
      4. 8.3.4 Smart Gate Driver
        1. Functional Block Diagram
        2. Slew Rate Control (IDRIVE)
        3. Gate Drive State Machine (TDRIVE)
        4. Propagation Delay Reduction (PDR)
          1. PDR Pre-Charge/Pre-Discharge Control Loop Operation Details
            1. PDR Pre-Charge/Pre-Discharge Setup
          2. PDR Post-Charge/Post-Discharge Control Loop Operation Details
            1. PDR Post-Charge/Post-Discharge Setup
          3. Detecting Drive and Freewheel MOSFET
        5. Automatic Duty Cycle Compensation (DCC)
        6. Closed Loop Slew Time Control (STC)
          1. STC Control Loop Setup
      5. 8.3.5 Tripler (Dual-Stage) Charge Pump
      6. 8.3.6 Wide Common-Mode Current Shunt Amplifiers
      7. 8.3.7 Pin Diagrams
        1. Logic Level Input Pin (INx/ENx, INx/PHx, nSLEEP, nSCS, SCLK, SDI)
        2. Logic Level Push Pull Output (SDO)
        3. Logic Level Multi-Function Pin (DRVOFF/nFLT)
        4. Quad-Level Input (GAIN, MODE)
        5. Six-Level Input (IDRIVE, VDS)
      8. 8.3.8 Protection and Diagnostics
        1.  Gate Driver Disable (DRVOFF/nFLT and EN_DRV)
        2.  Low IQ Powered Off Braking (POB, BRAKE)
        3.  Fault Reset (CLR_FLT)
        4.  DVDD Logic Supply Power on Reset (DVDD_POR)
        5.  PVDD Supply Undervoltage Monitor (PVDD_UV)
        6.  PVDD Supply Overvoltage Monitor (PVDD_OV)
        7.  VCP Charge Pump Undervoltage Lockout (VCP_UV)
        8.  MOSFET VDS Overcurrent Protection (VDS_OCP)
        9.  Gate Driver Fault (VGS_GDF)
        10. Thermal Warning (OTW)
        11. Thermal Shutdown (OTSD)
        12. Offline Short Circuit and Open Load Detection (OOL and OSC)
        13. Watchdog Timer
        14. Fault Detection and Response Summary Table
    4. 8.4 Device Functional Modes
      1. 8.4.1 Inactive or Sleep State
      2. 8.4.2 Standby State
      3. 8.4.3 Operating State
    5. 8.5 Programming
      1. 8.5.1 SPI Interface
      2. 8.5.2 SPI Format
      3. 8.5.3 SPI Interface for Multiple Slaves
        1. SPI Interface for Multiple Slaves in Daisy Chain
    6. 8.6 Register Maps
      1. 8.6.1 DRV8718-Q1 Register Map
      2. 8.6.2 DRV8714-Q1 Register Map
      3. 8.6.3 DRV8718-Q1 Register Descriptions
        1. DRV8718-Q1_STATUS Registers
        2. DRV8718-Q1_CONTROL Registers
        3. DRV8718-Q1_CONTROL_ADV Registers
        4. DRV8718-Q1_STATUS_ADV Registers
      4. 8.6.4 DRV8714-Q1 Register Descriptions
        1. DRV8714-Q1_STATUS Registers
        2. DRV8714-Q1_CONTROL Registers
        3. DRV8714-Q1_CONTROL_ADV Registers
        4. DRV8714-Q1_STATUS_ADV Registers
  9. Application Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. Gate Driver Configuration
          1. VCP Load Calculation Example
          2. IDRIVE Calculation Example
          3. tDRIVE Calculation Example
          4. Maximum PWM Switching Frequency
        2. Current Shunt Amplifier Configuration
        3. Power Dissipation
      3. 9.2.3 Application Curves
    3. 9.3 Initialization
  10. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance Sizing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device Documentation and Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documents
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Slew Rate Control (IDRIVE)

The IDRIVE component of the smart gate drive architecture implements adjustable gate drive current control to adjust the external MOSFET VDS slew rate. This is achieved by implementing adjustable pull up (IDRVP) and pull down (IDRVN) current sources for the internal gate driver architecture.

The external MOSFET VDS slew rates are a critical factor for optimizing radiated and conducted emissions, diode reverse recovery, dV/dt parasitic gate coupling, and overvoltage or undervoltage transients on the switch-node of the half-bridge. IDRIVE operates on the principle that the VDS slew rates are predominantly determined by the rate of the gate charge (or gate current) delivered during the MOSFET QGD or Miller charging region. By allowing the gate driver to adjust the gate current, it can effectively control the slew rate of the external power MOSFETs.

IDRIVE allows the DRV871x-Q1 to dynamically change the gate driver current setting through the IDRVP_x and IDRVN_x SPI registers or IDRIVE pin on H/W interface devices. The device provides 16 settings between the 0.5-mA and 62-mA range for the source and sink currents as shown in Table 8-16. The peak gate drive current is available for the tDRIVE duration. After the MOSFET is switched and the tDRIVE duration expires, the gate driver switches to a hold current (IHOLD) for the pull up source current to limit the output current in case of a short circuit condition and to improve the efficiency of the driver.

On SPI interface devices, the IDRV_LOx control register allows for 16 settings <0.5mA if extremely low slew rate control is required.

Table 8-16 IDRIVE Source (IDRVP) and Sink (IDRVN) Current
IDRVP_x / IDRVN_xGate Source / Sink Current
IDRV_LOx = 0bIDRV_LOx = 1b
0000b0.5 mA50 µA
0001b1 mA110 µA
0010b2 mA170 µA
0011b3 mA230 µA
0100b4 mA290 µA
0101b5 mA350 µA
0110b6 mA410 µA
0111b7 mA600 µA
1000b8 mA725 µA
1001b12 mA850 µA
1010b16 mA1 mA
1011b20 mA1.2 mA
1100b24 mA1.4 mA
1101b31 mA1.6 mA
1110b48 mA1.8 mA
1111b62 mA2.3 mA