SLVSEA2B August   2020  – June 2021 DRV8714-Q1 , DRV8718-Q1

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1. 6.1 VQFN (RVJ) 56-Pin Package and Pin Functions
    2. 6.2 VQFN (RHA) 40-Pin Package and Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 External Components
      2. 8.3.2 Device Interface Variants
        1. 8.3.2.1 Serial Peripheral Interface (SPI)
        2. 8.3.2.2 Hardware (H/W)
      3. 8.3.3 Input PWM Control Modes
        1. 8.3.3.1 Half-Bridge Control Scheme With Input PWM Mapping
          1. 8.3.3.1.1 DRV8718-Q1 Half-Bridge Control
          2. 8.3.3.1.2 DRV8714-Q1 Half-Bridge Control
        2. 8.3.3.2 H-Bridge Control
          1. 8.3.3.2.1 DRV8714-Q1 H-Bridge Control
        3. 8.3.3.3 Split HS and LS Solenoid Control
          1. 8.3.3.3.1 DRV8714-Q1 Split HS and LS Solenoid Control
      4. 8.3.4 Smart Gate Driver
        1. 8.3.4.1 Functional Block Diagram
        2. 8.3.4.2 Slew Rate Control (IDRIVE)
        3. 8.3.4.3 Gate Drive State Machine (TDRIVE)
        4. 8.3.4.4 Propagation Delay Reduction (PDR)
          1. 8.3.4.4.1 PDR Pre-Charge/Pre-Discharge Control Loop Operation Details
            1. 8.3.4.4.1.1 PDR Pre-Charge/Pre-Discharge Setup
          2. 8.3.4.4.2 PDR Post-Charge/Post-Discharge Control Loop Operation Details
            1. 8.3.4.4.2.1 PDR Post-Charge/Post-Discharge Setup
          3. 8.3.4.4.3 Detecting Drive and Freewheel MOSFET
        5. 8.3.4.5 Automatic Duty Cycle Compensation (DCC)
        6. 8.3.4.6 Closed Loop Slew Time Control (STC)
          1. 8.3.4.6.1 STC Control Loop Setup
      5. 8.3.5 Tripler (Dual-Stage) Charge Pump
      6. 8.3.6 Wide Common-Mode Current Shunt Amplifiers
      7. 8.3.7 Pin Diagrams
        1. 8.3.7.1 Logic Level Input Pin (INx/ENx, INx/PHx, nSLEEP, nSCS, SCLK, SDI)
        2. 8.3.7.2 Logic Level Push Pull Output (SDO)
        3. 8.3.7.3 Logic Level Multi-Function Pin (DRVOFF/nFLT)
        4. 8.3.7.4 Quad-Level Input (GAIN, MODE)
        5. 8.3.7.5 Six-Level Input (IDRIVE, VDS)
      8. 8.3.8 Protection and Diagnostics
        1. 8.3.8.1  Gate Driver Disable (DRVOFF/nFLT and EN_DRV)
        2. 8.3.8.2  Low IQ Powered Off Braking (POB, BRAKE)
        3. 8.3.8.3  Fault Reset (CLR_FLT)
        4. 8.3.8.4  DVDD Logic Supply Power on Reset (DVDD_POR)
        5. 8.3.8.5  PVDD Supply Undervoltage Monitor (PVDD_UV)
        6. 8.3.8.6  PVDD Supply Overvoltage Monitor (PVDD_OV)
        7. 8.3.8.7  VCP Charge Pump Undervoltage Lockout (VCP_UV)
        8. 8.3.8.8  MOSFET VDS Overcurrent Protection (VDS_OCP)
        9. 8.3.8.9  Gate Driver Fault (VGS_GDF)
        10. 8.3.8.10 Thermal Warning (OTW)
        11. 8.3.8.11 Thermal Shutdown (OTSD)
        12. 8.3.8.12 Offline Short Circuit and Open Load Detection (OOL and OSC)
        13. 8.3.8.13 Watchdog Timer
        14. 8.3.8.14 Fault Detection and Response Summary Table
    4. 8.4 Device Functional Modes
      1. 8.4.1 Inactive or Sleep State
      2. 8.4.2 Standby State
      3. 8.4.3 Operating State
    5. 8.5 Programming
      1. 8.5.1 SPI Interface
      2. 8.5.2 SPI Format
      3. 8.5.3 SPI Interface for Multiple Slaves
        1. 8.5.3.1 SPI Interface for Multiple Slaves in Daisy Chain
    6. 8.6 Register Maps
      1. 8.6.1 DRV8718-Q1 Register Map
      2. 8.6.2 DRV8714-Q1 Register Map
      3. 8.6.3 DRV8718-Q1 Register Descriptions
        1. 8.6.3.1 DRV8718-Q1_STATUS Registers
        2. 8.6.3.2 DRV8718-Q1_CONTROL Registers
        3. 8.6.3.3 DRV8718-Q1_CONTROL_ADV Registers
        4. 8.6.3.4 DRV8718-Q1_STATUS_ADV Registers
      4. 8.6.4 DRV8714-Q1 Register Descriptions
        1. 8.6.4.1 DRV8714-Q1_STATUS Registers
        2. 8.6.4.2 DRV8714-Q1_CONTROL Registers
        3. 8.6.4.3 DRV8714-Q1_CONTROL_ADV Registers
        4. 8.6.4.4 DRV8714-Q1_STATUS_ADV Registers
  9. Application Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Gate Driver Configuration
          1. 9.2.2.1.1 VCP Load Calculation Example
          2. 9.2.2.1.2 IDRIVE Calculation Example
          3. 9.2.2.1.3 tDRIVE Calculation Example
          4. 9.2.2.1.4 Maximum PWM Switching Frequency
        2. 9.2.2.2 Current Shunt Amplifier Configuration
        3. 9.2.2.3 Power Dissipation
      3. 9.2.3 Application Curves
    3. 9.3 Initialization
  10. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance Sizing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device Documentation and Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documents
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

DRV8718-Q1_STATUS_ADV Registers

Table 8-88 lists the DRV8718-Q1_STATUS_ADV registers. All register offset addresses not listed in Table 8-88 should be considered as reserved locations and the register contents should not be modified.

Table 8-88 DRV8718-Q1_STATUS_ADV Registers
Address Acronym Register Name Section
3Ch SGD_STAT1 Half-bridge 1-8 current polarity indicators Go
3Dh SGD_STAT2 Half-bridge 1-8 PDR underflow and overflow indicators Go
3Eh SGD_STAT3 Half-bridge 1-8 STC fault indicator Go

Complex bit access types are encoded to fit into small table cells. Table 8-89 shows the codes that are used for access types in this section.

Table 8-89 DRV8718-Q1_STATUS_ADV Access Type Codes
Access Type Code Description
Read Type
R R Read
Reset or Default Value
- n Value after reset or the default value

6.3.4.1 SGD_STAT1 Register (Address = 3Ch) [Reset = 0h]

SGD_STAT1 is shown in Figure 8-95 and described in Table 8-90.

Return to the Summary Table.

Status registers indicating current polarity for half-bridges 1-8.

Figure 8-95 SGD_STAT1 Register
7 6 5 4 3 2 1 0
IDIR_12 IDIR_34 IDIR_56 IDIR_78 IDIR_WARN_12 IDIR_WARN_34 IDIR_WARN_56 IDIR_WARN_78
R-0b R-0b R-0b R-0b R-0b R-0b R-0b R-0b
Table 8-90 SGD_STAT1 Register Field Descriptions
Bit Field Type Reset Description
7 IDIR_12 R 0b Indicated current direction for half-bridge 1 and 2.
6 IDIR_34 R 0b Indicated current direction for half-bridge 3 and 4.
5 IDIR_56 R 0b Indicated current direction for half-bridge 5 and 6.
4 IDIR_78 R 0b Indicated current direction for half-bridge 7 and 8.
3 IDIR_WARN_12 R 0b Indicates unknown current direction for half-bridge 1 and 2.
2 IDIR_WARN_34 R 0b Indicates unknown current direction for half-bridge 3 and 4.
1 IDIR_WARN_56 R 0b Indicates unknown current direction for half-bridge 5 and 6.
0 IDIR_WARN_78 R 0b Indicates unknown current direction for half-bridge 7 and 8.

6.3.4.2 SGD_STAT2 Register (Address = 3Dh) [Reset = 0h]

SGD_STAT2 is shown in Figure 8-96 and described in Table 8-91.

Return to the Summary Table.

Status registers indicating underflow and overflow in PDR loop control for half-bridges 1-8.

Figure 8-96 SGD_STAT2 Register
7 6 5 4 3 2 1 0
PCHR_WARN_12 PCHR_WARN_34 PCHR_WARN_56 PCHR_WARN_78 PDCHR_WARN_12 PDCHR_WARN_34 PDCHR_WARN_56 PDCHR_WARN_78
R-0b R-0b R-0b R-0b R-0b R-0b R-0b R-0b
Table 8-91 SGD_STAT2 Register Field Descriptions
Bit Field Type Reset Description
7 PCHR_WARN_12 R 0b Indicates pre-charge underflow or overflow fault for half-bridge 1 and 2.
6 PCHR_WARN_34 R 0b Indicates pre-charge underflow or overflow fault for half-bridge 3 and 4.
5 PCHR_WARN_56 R 0b Indicates pre-charge underflow or overflow fault for half-bridge 5 and 6.
4 PCHR_WARN_78 R 0b Indicates pre-charge underflow or overflow fault for half-bridge 7 and 8.
3 PDCHR_WARN_12 R 0b Indicates pre-discharge underflow or overflow fault for half-bridge 1 and 2.
2 PDCHR_WARN_34 R 0b Indicates pre-discharge underflow or overflow fault for half-bridge 3 and 4.
1 PDCHR_WARN_56 R 0b Indicates pre-discharge underflow or overflow fault for half-bridge 5 and 6.
0 PDCHR_WARN_78 R 0b Indicates pre-discharge underflow or overflow fault for half-bridge 7 and 8.

6.3.4.3 SGD_STAT3 Register (Address = 3Eh) [Reset = 0h]

SGD_STAT3 is shown in Figure 8-97 and described in Table 8-92.

Return to the Summary Table.

Status register indicator STC rise and fall time overflow for half-bridges 1-8.

Figure 8-97 SGD_STAT3 Register
7 6 5 4 3 2 1 0
STC_WARN_F_12 STC_WARN_F_34 STC_WARN_F_56 STC_WARN_F_78 STC_WARN_R_12 STC_WARN_R_34 STC_WARN_R_56 STC_WARN_R_78
R-0b R-0b R-0b R-0b R-0b R-0b R-0b R-0b
Table 8-92 SGD_STAT3 Register Field Descriptions
Bit Field Type Reset Description
7 STC_WARN_F_12 R 0b Indicates falling slew time TDRV overflow for half-bridge 1 and 2.
6 STC_WARN_F_34 R 0b Indicates falling slew time TDRV overflow for half-bridge 3 and 4.
5 STC_WARN_F_56 R 0b Indicates falling slew time TDRV overflow for half-bridge 5 and 6.
4 STC_WARN_F_78 R 0b Indicates falling slew time TDRV overflow for half-bridge 7 and 8.
3 STC_WARN_R_12 R 0b Indicates rising slew time TDRV overflow for half-bridge 1 and 2.
2 STC_WARN_R_34 R 0b Indicates rising slew time TDRV overflow for half-bridge 3 and 4.
1 STC_WARN_R_56 R 0b Indicates rising slew time TDRV overflow for half-bridge 5 and 6.
0 STC_WARN_R_78 R 0b Indicates rising slew time TDRV overflow for half-bridge 7 and 8.