The DRV8714-Q1 controls the four half-bridge gate drivers through a combination of direct PWM, PWM multiplexers, and SPI control registers. The half-bridge control mode can be enabled by setting BRG_MODE = 00b on SPI interface variants or the MODE pin to level 1 on H/W interface variants. On SPI interface variants, the HBx_CTRL (half-bridge control) SPI register is used to control the half-bridge gate driver output state. The different control states for the gate drivers are shown in Table 8-6. Any unused half-bridge drivers should be left disconnected and in the high-impedance (Hi-Z) output state. On H/W interface variants, the device defaults to direct PWM control from the associated INx/ENx input pins.
The DRV8714-Q1 PWM inputs pins (IN1/EN1, IN2/PH1. IN3/EN2, IN4/PH2) can be used to set the PWM frequency and duty cycle for the assigned output. If high frequency or precise duty cycle PWM control is not required, the four half-bridge gate drivers can be controlled directly through the HBx_CTRL SPI control register on SPI interface variants.
The DRV8714-Q1 can also be used to control individual high-side or low-side external MOSFETs instead of a half-bridge. In this setup, simply leave the unused GHx/GLx driver of the half-bridge disconnected. Only passive freewheeling should be utilized if PWM control is needed in this setup.
|HBx_CTRL (1-4)||Gate Driver State||GHx (1-4)||GLx (1-4)||SHx (1-4)|
|00b||High Impedance (Hi-Z)||L||L||Hi-Z|
|01b||Drive Low-Side (L)||L||H||L|
|10b||Drive High-Side (H)||H||L||H|
|11b||Drive PWM (PWM)||Table 8-8||Table 8-8||Table 8-8|
In PWM control mode, the half-bridge gate drivers can be controlled directly by any of 4 independent PWM control inputs (IN1, IN2, IN3, IN4) as shown in Table 8-4. On H/W interface variants, the PWM control inputs map directly to their associated output number.
PWM mapping helps reduce the number of required PWM resources and pins from the external controller when utilizing motor groups or zone control schemes while still allowing for fine PWM frequency and duty cycle control. Each PWM input pin can be mapped to as many half-bridge drivers as desired. The input PWM signal can actively drive the high-side or low-side MOSFET of the half-bridge (based on PWMx_HL control register), with the opposite MOSFET in the half-bridge being controlled accordingly based on the freewheeling setting. Either active or passive freewheeling can be configured by the PWMx_FW control register. On H/W interface variants, the device is configured for high-side PWM drive with active freewheeling.
The following steps should be taken to modify the PWM mapping scheme during driver operation.
|HBx_PWM (1-4)||Input PWM Source|
|HBx_PWM (1-4)||HBx_HL (1-4)||HBx_FW (1-4)||Gate Driver State||GHx (1-4)||GLx (1-4)||SHx (1-4)|