SLVSEA2B August   2020  – June 2021 DRV8714-Q1 , DRV8718-Q1

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1. 6.1 VQFN (RVJ) 56-Pin Package and Pin Functions
    2. 6.2 VQFN (RHA) 40-Pin Package and Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 External Components
      2. 8.3.2 Device Interface Variants
        1. 8.3.2.1 Serial Peripheral Interface (SPI)
        2. 8.3.2.2 Hardware (H/W)
      3. 8.3.3 Input PWM Control Modes
        1. 8.3.3.1 Half-Bridge Control Scheme With Input PWM Mapping
          1. 8.3.3.1.1 DRV8718-Q1 Half-Bridge Control
          2. 8.3.3.1.2 DRV8714-Q1 Half-Bridge Control
        2. 8.3.3.2 H-Bridge Control
          1. 8.3.3.2.1 DRV8714-Q1 H-Bridge Control
        3. 8.3.3.3 Split HS and LS Solenoid Control
          1. 8.3.3.3.1 DRV8714-Q1 Split HS and LS Solenoid Control
      4. 8.3.4 Smart Gate Driver
        1. 8.3.4.1 Functional Block Diagram
        2. 8.3.4.2 Slew Rate Control (IDRIVE)
        3. 8.3.4.3 Gate Drive State Machine (TDRIVE)
        4. 8.3.4.4 Propagation Delay Reduction (PDR)
          1. 8.3.4.4.1 PDR Pre-Charge/Pre-Discharge Control Loop Operation Details
            1. 8.3.4.4.1.1 PDR Pre-Charge/Pre-Discharge Setup
          2. 8.3.4.4.2 PDR Post-Charge/Post-Discharge Control Loop Operation Details
            1. 8.3.4.4.2.1 PDR Post-Charge/Post-Discharge Setup
          3. 8.3.4.4.3 Detecting Drive and Freewheel MOSFET
        5. 8.3.4.5 Automatic Duty Cycle Compensation (DCC)
        6. 8.3.4.6 Closed Loop Slew Time Control (STC)
          1. 8.3.4.6.1 STC Control Loop Setup
      5. 8.3.5 Tripler (Dual-Stage) Charge Pump
      6. 8.3.6 Wide Common-Mode Current Shunt Amplifiers
      7. 8.3.7 Pin Diagrams
        1. 8.3.7.1 Logic Level Input Pin (INx/ENx, INx/PHx, nSLEEP, nSCS, SCLK, SDI)
        2. 8.3.7.2 Logic Level Push Pull Output (SDO)
        3. 8.3.7.3 Logic Level Multi-Function Pin (DRVOFF/nFLT)
        4. 8.3.7.4 Quad-Level Input (GAIN, MODE)
        5. 8.3.7.5 Six-Level Input (IDRIVE, VDS)
      8. 8.3.8 Protection and Diagnostics
        1. 8.3.8.1  Gate Driver Disable (DRVOFF/nFLT and EN_DRV)
        2. 8.3.8.2  Low IQ Powered Off Braking (POB, BRAKE)
        3. 8.3.8.3  Fault Reset (CLR_FLT)
        4. 8.3.8.4  DVDD Logic Supply Power on Reset (DVDD_POR)
        5. 8.3.8.5  PVDD Supply Undervoltage Monitor (PVDD_UV)
        6. 8.3.8.6  PVDD Supply Overvoltage Monitor (PVDD_OV)
        7. 8.3.8.7  VCP Charge Pump Undervoltage Lockout (VCP_UV)
        8. 8.3.8.8  MOSFET VDS Overcurrent Protection (VDS_OCP)
        9. 8.3.8.9  Gate Driver Fault (VGS_GDF)
        10. 8.3.8.10 Thermal Warning (OTW)
        11. 8.3.8.11 Thermal Shutdown (OTSD)
        12. 8.3.8.12 Offline Short Circuit and Open Load Detection (OOL and OSC)
        13. 8.3.8.13 Watchdog Timer
        14. 8.3.8.14 Fault Detection and Response Summary Table
    4. 8.4 Device Functional Modes
      1. 8.4.1 Inactive or Sleep State
      2. 8.4.2 Standby State
      3. 8.4.3 Operating State
    5. 8.5 Programming
      1. 8.5.1 SPI Interface
      2. 8.5.2 SPI Format
      3. 8.5.3 SPI Interface for Multiple Slaves
        1. 8.5.3.1 SPI Interface for Multiple Slaves in Daisy Chain
    6. 8.6 Register Maps
      1. 8.6.1 DRV8718-Q1 Register Map
      2. 8.6.2 DRV8714-Q1 Register Map
      3. 8.6.3 DRV8718-Q1 Register Descriptions
        1. 8.6.3.1 DRV8718-Q1_STATUS Registers
        2. 8.6.3.2 DRV8718-Q1_CONTROL Registers
        3. 8.6.3.3 DRV8718-Q1_CONTROL_ADV Registers
        4. 8.6.3.4 DRV8718-Q1_STATUS_ADV Registers
      4. 8.6.4 DRV8714-Q1 Register Descriptions
        1. 8.6.4.1 DRV8714-Q1_STATUS Registers
        2. 8.6.4.2 DRV8714-Q1_CONTROL Registers
        3. 8.6.4.3 DRV8714-Q1_CONTROL_ADV Registers
        4. 8.6.4.4 DRV8714-Q1_STATUS_ADV Registers
  9. Application Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Gate Driver Configuration
          1. 9.2.2.1.1 VCP Load Calculation Example
          2. 9.2.2.1.2 IDRIVE Calculation Example
          3. 9.2.2.1.3 tDRIVE Calculation Example
          4. 9.2.2.1.4 Maximum PWM Switching Frequency
        2. 9.2.2.2 Current Shunt Amplifier Configuration
        3. 9.2.2.3 Power Dissipation
      3. 9.2.3 Application Curves
    3. 9.3 Initialization
  10. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance Sizing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device Documentation and Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documents
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
DRV8714-Q1 Half-Bridge Control

The DRV8714-Q1 controls the four half-bridge gate drivers through a combination of direct PWM, PWM multiplexers, and SPI control registers. The half-bridge control mode can be enabled by setting BRG_MODE = 00b on SPI interface variants or the MODE pin to level 1 on H/W interface variants. On SPI interface variants, the HBx_CTRL (half-bridge control) SPI register is used to control the half-bridge gate driver output state. The different control states for the gate drivers are shown in Table 8-6. Any unused half-bridge drivers should be left disconnected and in the high-impedance (Hi-Z) output state. On H/W interface variants, the device defaults to direct PWM control from the associated INx/ENx input pins.

The DRV8714-Q1 PWM inputs pins (IN1/EN1, IN2/PH1. IN3/EN2, IN4/PH2) can be used to set the PWM frequency and duty cycle for the assigned output. If high frequency or precise duty cycle PWM control is not required, the four half-bridge gate drivers can be controlled directly through the HBx_CTRL SPI control register on SPI interface variants.

The DRV8714-Q1 can also be used to control individual high-side or low-side external MOSFETs instead of a half-bridge. In this setup, simply leave the unused GHx/GLx driver of the half-bridge disconnected. Only passive freewheeling should be utilized if PWM control is needed in this setup.

Table 8-6 Half-Bridge SPI Register Control (HBx_CTRL)
HBx_CTRL (1-4)Gate Driver StateGHx (1-4)GLx (1-4)SHx (1-4)
00bHigh Impedance (Hi-Z)LLHi-Z
01bDrive Low-Side (L)LHL
10bDrive High-Side (H)HLH
11bDrive PWM (PWM)Table 8-8Table 8-8Table 8-8

In PWM control mode, the half-bridge gate drivers can be controlled directly by any of 4 independent PWM control inputs (IN1, IN2, IN3, IN4) as shown in Table 8-4. On H/W interface variants, the PWM control inputs map directly to their associated output number.

PWM mapping helps reduce the number of required PWM resources and pins from the external controller when utilizing motor groups or zone control schemes while still allowing for fine PWM frequency and duty cycle control. Each PWM input pin can be mapped to as many half-bridge drivers as desired. The input PWM signal can actively drive the high-side or low-side MOSFET of the half-bridge (based on PWMx_HL control register), with the opposite MOSFET in the half-bridge being controlled accordingly based on the freewheeling setting. Either active or passive freewheeling can be configured by the PWMx_FW control register. On H/W interface variants, the device is configured for high-side PWM drive with active freewheeling.

The following steps should be taken to modify the PWM mapping scheme during driver operation.

  • Set active half-bridge to Hi-Z mode through HBx_CTRL.
  • Set new target half-bridge to Hi-Z mode through HBx_CTRL.
  • HBx_PWM mapping should be updated from the old target to the new target half-bridge.
  • Set new target half-bridge drive MOSFET (PWMx_HL) and freewheeling settings (PWMx_FW).
  • Set new target half-bridge to PWM mode through HBx_CTRL.

Table 8-7 Half-Bridge PWM Mapping (PWMx_MAP)
PWM Mapping
HBx_PWM (1-4) Input PWM Source
00bIN1
01bIN2
10bIN3
11bIN4
Table 8-8 Half-Bridge PWM Control (PWMx_HL and PWMx_FW)
HBx_PWM (1-4)HBx_HL (1-4)HBx_FW (1-4)Gate Driver StateGHx (1-4)GLx (1-4)SHx (1-4)
PWMx00PWM High-Side
Active FW
PWMx!PWMxPWMx
1PWM Low-Side
Active FW
!PWMxPWMx!PWMx
01PWM High-Side
Passive FW
PWMxLPWMx
1PWM Low-Side
Passive FW
LPWMx!PWMx
GUID-1C283EF0-E0DA-475D-9492-3F62B4EEE407-low.gifFigure 8-7 PWM Mapping Example 1
GUID-9A6AB4DF-0975-490F-A805-0D7784AD8FFA-low.gifFigure 8-8 PWM Mapping Example 2