SBOSA39A April   2025  – October 2025 THS3470

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics ±VS = ±30V
    6. 5.6 Electrical Characteristics ±VS = ±20V
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Output Current Limit
      2. 6.3.2 Output Current Enable
      3. 6.3.3 Over Temperature Flag
      4. 6.3.4 Output Current Flags
      5. 6.3.5 Output Current Monitoring
      6. 6.3.6 Die Temperature Monitoring
      7. 6.3.7 External Compensation
    4. 6.4 Device Functional Modes
      1. 6.4.1 Power Modes
      2. 6.4.2 Choosing a Feedback Resistor
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 High-Voltage, High-Precision, Composite Amplifier
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
      2. 7.2.2 120V Bootstrap Amplifier
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
        3. 7.2.2.3 Application Performance Plots
    3. 7.3 Short Circuit Protection
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Thermal Considerations
        1. 7.5.1.1 Top-Side Cooling Benefits
        2. 7.5.1.2 THS3470 Safe Operating Area
      2. 7.5.2 Layout Guidelines
      3. 7.5.3 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 TAPE AND REEL INFORMATION

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • REB|42
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.1 Output Current Limit

The THS3470 features two pins, ISRC_LIMIT and ISNK_LIMIT, that set output current limits through the VOUT pin. ISRC_LIMIT controls the VOUT sourcing current limit (current exiting the device output, IOUT source) from 200mA to 1.5A. ISNK_LIMIT controls the VOUT sinking current limit (current entering the device output, IOUT sink) from 200mA to 1.5A.

Note: To enable the output sourcing limit, governed by the ISRC_LIMIT pin, the ISRC_LIMIT_EN pin must be low. To enable the output sinking limit, governed by the ISNK_LIMIT pin, the ISNK_LIMIT_EN pin must be low.
CAUTION: If ISRC_LIMIT or ISNK_LIMIT is left unconnected, the device defaults to a 2.1A current limit. If ISRC_LIMIT or ISNK_LIMIT is set for less than 200mA, the device enters a 2.1A current limit. Failure to properly regulate the current can increase the junction temperature beyond the absolute maximum junction temperature and cause damage to the device.

To statically set the output sourcing limit, connect resistor RSRC_LIMIT from ISRC_LIMIT and VEE. To statically set the output sinking limit, connect resistor RSNK_LIMIT from ISNK_LIMIT and VCC. Figure 6-1 shows an example of these connections, the equations that govern the current limit are shown in Equation 1 and Equation 2, and the resistor values for typical applications are shown in Table 6-1.

Equation 1. R S R C _ L I M I T =   V M I D -   V E E × 2048 I O U T   S o u r c e   L i m i t   ( A ) - 720
Equation 2. RSNK_LIMIT= VCC-VMID×2048IOUT Sink Limit (A)-720
THS3470 Statically Set Output Current Limit Figure 6-1 Statically Set Output Current Limit
Table 6-1 Typical Resistor Values for Statically Set Output Current Limit
VS (V) IOUT Source/Sink Limit (A) RSNK_LIMIT/RSRC_LIMIT (Ω)
60 0.2 306k
60 0.5 122k
60 1 60k
60 1.5 40k
40 0.2 204k
40 0.5 81k
40 1 40k
40 1.5 27k

Alternatively, the current limit pins can be adjusted through a voltage digital-to-analog converter (DAC), or other low impedance voltage source, as shown in Figure 6-2. This method helps provide programmable control of the output current limit if the application requires. The equation that governs the current limit for this method is shown in Equation 3 and Table 6-3 shows examples of dynamically configuring the current limit.

Equation 3. V D A C   V = I O U T ( A ) ×   4.5 k Ω 2048
THS3470 Dynamically Set Output Current Limit Figure 6-2 Dynamically Set Output Current Limit
Table 6-2 Example DAC Voltages for Dynamically Set Output Current Limit
VOUT CURRENT LIMIT (mA) ILIMIT_SRC/SNK (μA) DAC VOLTAGE, VDAC (V)
200 97.65 0.439
500 24.41 1.099
1000 488.28 2.197
1500 732.42 3.296
CAUTION: Make sure that the ISNK_LIMIT voltage is greater than the VMID voltage, and that the ISRC_LIMIT voltage is less than the VMID voltage. Failure to adhere to this caution can result in damage to the device. Additionally, the VMID pin must be externally buffered to be used as a power supply.