SBOSA39A April   2025  – October 2025 THS3470

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics ±VS = ±30V
    6. 5.6 Electrical Characteristics ±VS = ±20V
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Output Current Limit
      2. 6.3.2 Output Current Enable
      3. 6.3.3 Over Temperature Flag
      4. 6.3.4 Output Current Flags
      5. 6.3.5 Output Current Monitoring
      6. 6.3.6 Die Temperature Monitoring
      7. 6.3.7 External Compensation
    4. 6.4 Device Functional Modes
      1. 6.4.1 Power Modes
      2. 6.4.2 Choosing a Feedback Resistor
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 High-Voltage, High-Precision, Composite Amplifier
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
      2. 7.2.2 120V Bootstrap Amplifier
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
        3. 7.2.2.3 Application Performance Plots
    3. 7.3 Short Circuit Protection
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Thermal Considerations
        1. 7.5.1.1 Top-Side Cooling Benefits
        2. 7.5.1.2 THS3470 Safe Operating Area
      2. 7.5.2 Layout Guidelines
      3. 7.5.3 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 TAPE AND REEL INFORMATION

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • REB|42
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

Figure 4-1 REB Package, 42-Pin VQFN (Top View)
Pin Functions
PIN TYPE DESCRIPTION
NAME NO.
COMP 14 Input Internal compensation pin. Leave unconnected, with ground cutout, by default. See Section 6.3.7 for more details about pin operation.
DGND 33, 34 Input Digital ground
DIE_TEMP 12, 13 Output Die temperature output. The pin outputs 1.6V at 25°C by default. See Section 6.3.6 for more details about pin operation.
FB 35 Output Input side feedback pin
IN− 37 Input Inverting input
IN+ 40 Input Noninverting input
IOUT_MONITOR 11 Output Output current monitor. Must be connected with 10kΩ pull-up and pull-down resistor by default. See Section 6.3.5 for more details about pin operation.
ISNK_FLAG 6 Output Output current sink flag. Internally pulled-up to VDD when device is under the set sink current limit by default. See Section 6.3.4 for more details about pin operation.
ISNK_LIMIT 7 Input Output current sink limit. Connect pull-up resistor to VCC by default. See Section 6.3.1 for more details about pin operation.
ISNK_LIMIT_EN 4 Input Output current sink limit control. Internally pulled-up to VDD by default, resulting in no current limit while VOUT is sinking current. See Section 6.3.2 for more details about pin operation.
ISRC_FLAG 5 Output Output current source flag. Internally pulled-up to VDD when device is under the set source current limit by default. See Section 6.3.4 for more details about pin operation.
ISRC_LIMIT 28 Input Output current source limit. Connect pull-down resistor to VEE by default. See Section 6.3.1 for more details about pin operation.
ISRC_LIMIT_EN 3 Input Output current source limit control. Internally pulled-up to VDD by default, resulting in no current limit while VOUT is sourcing current. See Section 6.3.2 for more details about pin operation.
DNC 21, 24, 42 — Leave unconnected. Pin disconnected internally.
OVTEMP_FLAG 22, 23 Output Over Temperature Flag. Default logic low when device junction temperature is <165°C. See Section 6.3.3 for more pin details.
P0 31 Input Power-mode control, bit0. Internally pulled high to enable full bias mode. See Section 6.4.1 and Section 6.3.3 for more details about pin connections and performance.
P1 30 Input Power-mode control, bit1. Internally pulled high to enable full bias mode. See Section 6.4.1 and Section 6.3.3 for more details about pin connections and performance.
VCC 8, 9, 10, 25, 26, 27, 38, 39 Input Positive power supply. See Section 7.5.2 for bypass and layout suggestions.
VDD 32 Output Internally generated 5.0V digital power supply, relative to DGND. See Section 7.5.2 for bypass and layout suggestions.
VEE 15, 20, 29, 36, 41 Input Negative power supply. See Section 7.5.2 for bypass and layout suggestions.
VMID 1, 2 Output Midsupply buffered output, (VCC+VEE)/2. This pin must be buffered externally to use the VMID voltage as a power supply or voltage reference elsewhere in the design. See Section 7.5.2 for bypass and layout suggestions.
VOUT 16, 17, 18, 19 Output Amplifier output
Thermal Pad — Thermal pad. Internally tied to VEE