SBOSA39A April 2025 – October 2025 THS3470
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
The goal of this design is to optimize the output referred error of the THS3470 while preserving settling behavior using a composite loop. The input step for this design was chosen to be 5V to match a typical DAC to set the output voltage of the design. The output current (1A), output swing (40VPP), settling time (250ns), and output referred error (<0.1%) were all chosen based on the theoretical maximum performance of the OPA863A and THS3470. If higher precision is required, an OPA328, OPA387, or OPA365 can be used instead to reduce the output-referred error at the expense of settling time.
| PARAMETER | VALUE |
|---|---|
| Supply voltage | 60V |
| Input step size | 4V |
| Output step size | 40VPP (1A) |
| Output current | Up to 1A |
| Settling time (0.01%) | 250ns |
| Output-referred error | <0.1% |