Use individual power planes for
VCC, VEE, and ground nets on the PCB. While not required, creating individual
layers with minimal cutouts or traces for the power supplies and ground, as
shown in Section 7.5.3,
minimizes inductance and provides a large PCB area for current to flow.
Size traces and vias for VCC, VEE, and VOUT appropriately for the amount of
continuous current required for the application. Limit board temperature rise
based on IPC-2221 guidelines and PCB manufacturer recommendations. Increase
copper weight on layers and use external layers where possible to optimize board
space.
Place a 22μF tantalum or
electrolytic capacitor along with a 10μF X7R capacitor close to the VCC and VEE
supply sources. In addition, place 100nF capacitors as close to the THS3470
supply pins as possible. Minimize loop inductance for current return paths on
the bypass capacitors by placing multiple vias close to the pads of the
capacitor.
VMID requires 100nF C0G or NP0 bypass capacitors from VMID to VCC and VMID to
VEE. Place these capacitors as close to pin 1 as possible, with vias to the VCC,
VEE, and ground planes as close as possible to the capacitor pad.
Place 2.2nF capacitors on the VDD, ISRC_LIMIT_EN, ISNK_LIMIT_EN, P0, and P1
between the pin and DGND. Place these capacitors close to the THS3470, but not
at the expense of proximity for other components.
Place plane cutouts underneath
any traces or connections on the COMP or IN− pins to reduce parasitic
capacitance.
Place the isolation resistor for VOUT as close to the pin as possible to isolate
parasitic capacitance.
Place components connected to the
IN− and FB pins as close to the pin as possible. These nodes are sensitive to
parasitic capacitance and can cause oscillations if special care is not
taken.
Place the termination resistor as
close to the input of interest as possible. Add multiple vias on the ground
connection of the termination resistor to provide a clean current return path
and minimize inductance.