SBOSA39A April   2025  – October 2025 THS3470

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics ±VS = ±30V
    6. 5.6 Electrical Characteristics ±VS = ±20V
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Output Current Limit
      2. 6.3.2 Output Current Enable
      3. 6.3.3 Over Temperature Flag
      4. 6.3.4 Output Current Flags
      5. 6.3.5 Output Current Monitoring
      6. 6.3.6 Die Temperature Monitoring
      7. 6.3.7 External Compensation
    4. 6.4 Device Functional Modes
      1. 6.4.1 Power Modes
      2. 6.4.2 Choosing a Feedback Resistor
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 High-Voltage, High-Precision, Composite Amplifier
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
      2. 7.2.2 120V Bootstrap Amplifier
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
        3. 7.2.2.3 Application Performance Plots
    3. 7.3 Short Circuit Protection
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Thermal Considerations
        1. 7.5.1.1 Top-Side Cooling Benefits
        2. 7.5.1.2 THS3470 Safe Operating Area
      2. 7.5.2 Layout Guidelines
      3. 7.5.3 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 TAPE AND REEL INFORMATION

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • REB|42
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics ±VS = ±30V

at TA ≅ 25°C, AV = 10V/V, RF = 2kΩ, and RS = 5Ω (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AC PERFORMANCE
SSBW Small-signal bandwidth
(–3dB)		 VO = 2VPP RL = 100Ω 30 MHz
RS = 5Ω, CL = 1nF 20
LSBW Large-signal bandwidth
(–3dB)		 VO = 50VPP, < 1dB peaking RL = 100Ω 22 MHz
CL = 1nF (2) 7
SR Slew rate (peak) VO = 50VPP step RL = 100Ω 6500 V/µs
CL = 1nF 2600
Slew rate (20%–80%) VO = 50VPP step RL = 100Ω 3500
CL = 1nF 2000
Rise-and-fall time VO = 50V step RL = 100Ω 17 ns
CL = 1nF 22
Settling time To 0.1%, VO = 50V step RL = 100Ω 200 ns
CL = 1nF 375
HD2 2nd-harmonic distortion VO = 50VPP, RL = 100Ω f = 10MHz –47 dBc
f = 1MHz –80
f = 0.1MHz –91
VO = 50VPP, CL = 1nF f = 1MHz –80
f = 0.1MHz –87
HD3 3rd-harmonic distortion VO = 50VPP, RL = 100Ω f = 10MHz –43 dBc
f = 1MHz –67
f = 0.1MHz –75
VO = 50VPP, CL = 1nF f = 1MHz –61
f = 0.1MHz –71
en Voltage noise f > 100kHz 1.3 nV/√Hz
in+ Noninverting input-referred current noise f > 100kHz 31 pA/√Hz
in– Inverting input-referred current noise f > 100kHz 20 pA/√Hz
DC PERFORMANCE
ZOL Open-loop transimpedance gain VO = ±10V 4.5 5.5 MΩ
ZOL Open-loop transimpedance gain VO = ±10V, RL = 100Ω 4.1 MΩ
VOS Input offset voltage ±0.8 ±3.5 mV
Input offset voltage drift(1) TJ = –40°C to +125°C 5 µV/°C
IB– Inverting input bias current ±3 ±25 µA
Inverting input bias current drift TJ = –40°C to +125°C 100 nA/°C
IB+ Noninverting input bias current ±1 ±15 µA
Noninverting input bias current drift TJ = –40°C to +125°C 70 nA/°C
ZIN+ Noninverting input impedance 900 || 1.5 kΩ || pF
ZIN– Inverting input impedance 17 Ω
Input common-mode voltage VEE + 4 VCC – 4 V
INPUT
CMRR Common-mode rejection ratio f = dc, VICM = ±2V 67 dB
f = dc, VICM = ±25V 72
OUTPUT
HROUT Headroom to either supply RL = open ±4 ±5 V
HROUT Headroom to either supply RL = 100Ω ±4 ±5 V
IOUTLIN Linear output current RL = 5Ω, VO = ±10V, ZOL > 200kΩ, source and sink 1 1.35 A
IOUT Maximum current output 1.5 A
ZOUT DC output impedance Closed-loop 0.03 Ω
Open-loop output resistance Power down 11 kΩ
POWER SUPPLY
IQ Quiescent current Full bias, no load,
ISNK/ISRC_LIMIT = open		 31 32 mA
TJ = –40°C to +125°C 31 33
Full bias, no load,
ISNK/ISRC_LIMIT = 250mA		 29 30
TJ = –40°C to +125°C 29 31
Full bias, no load,
ISNK/ISRC LIMIT = 1A		 33 34
TJ = –40°C to +125°C 33 34
Power down, no load,
ISNK/ISRC_LIMIT = open		 14 16
TJ = –40°C to +125°C 14 16
PSRR Power-supply rejection ratio VS = ±12V to ±30V 76 81 dB
DIE TEMP MONITORING
OVTEMP_FLAG status flag low 165 °C
OVTEMP_FLAG status flag high 140 °C
TJ_SENSE Die temperature output voltage TJ = 25°C 1.55 V
TJ_SENSE temperature coefficient TJ = –40°C to +125°C 4.8 mV/°C
TJ_SENSE output impedance 50 kΩ
OUTPUT CURRENT MONITORING
IOUT_MONITOR response time  Referenced to midsupply, 10kΩ Pull-up (VCC) and 10kΩ Pull-down resistor (VEE) 20 µs
IOUT_MONITOR voltage Referenced to midsupply VMID - 2V VMID + 2V V
IOUT_MONITOR accuracy IOUT = ±200mA 15 %
IOUT = ±1A 30
CURRENT LIMIT MANAGEMENT
Output current limit Externally adjustable 200 1500 mA
Current limit response time  1 us
Current limit accuracy ILIMIT = ±200mA 5 15 %
ILIMIT = ±1A 5 15
DIGITAL INPUTS (P0, P1, ISRC_LIM_EN, ISNK_LIM_EN)
DGND voltage VEE VCC – 12 V
Digital input pin voltage With respect to DGND 0 5.0 V
Digital input pin logic threshold Logic high, with respect to DGND 1.3 1.5 V
Logic low, with respect to DGND 0.5 1.1
Digital input pin bias current VIN = 0V, with respect to DGND TJ = –40°C to +125°C -30 -13 30 µA
VIN = 5V, with respect to DGND TJ = –40°C to +125°C -30 -5 30
DIGITAL OUTPUTS (ISRC_FLAG, ISNK_FLAG, OVTEMP_FLAG)
Digital output pin voltage With respect to DGND 0 5.0 V
Digital output pin voltage high With respect to DGND 4.9 4.99 V
Digital output pin voltage low With respect to DGND 0.01 0.1 V
ISRC_FLAG response time 5 µs
ISNK_FLAG response time 5 µs
OVTEMP_FLAG response time 5 µs
(1) Current output based on electromigration limit, actual performance depends on system thermals.
(2) High capacitive load values, such as 1nF, limit the bandwidth as a result of large output current transients.