SBOSA39A April   2025  – October 2025 THS3470

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics ±VS = ±30V
    6. 5.6 Electrical Characteristics ±VS = ±20V
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Output Current Limit
      2. 6.3.2 Output Current Enable
      3. 6.3.3 Over Temperature Flag
      4. 6.3.4 Output Current Flags
      5. 6.3.5 Output Current Monitoring
      6. 6.3.6 Die Temperature Monitoring
      7. 6.3.7 External Compensation
    4. 6.4 Device Functional Modes
      1. 6.4.1 Power Modes
      2. 6.4.2 Choosing a Feedback Resistor
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 High-Voltage, High-Precision, Composite Amplifier
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
      2. 7.2.2 120V Bootstrap Amplifier
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
        3. 7.2.2.3 Application Performance Plots
    3. 7.3 Short Circuit Protection
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Thermal Considerations
        1. 7.5.1.1 Top-Side Cooling Benefits
        2. 7.5.1.2 THS3470 Safe Operating Area
      2. 7.5.2 Layout Guidelines
      3. 7.5.3 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 TAPE AND REEL INFORMATION

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • REB|42
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.2.2.2 Detailed Design Procedure

When designing with the THS3470, designers need to keep the total output current from both ac (capacitive) and dc (resistive) loads in mind. The maximum output current allowed for the THS3470 is 1.5A for dc current, but many applications demand an capacitive load drive at the device output (cables, parasitic capacitance, gate capacitance, etc) that can create large ac currents during large dv/dt steps or large signal sinusoid. Since the THS3470 slew rate is so high, 1kV/us in certain bootstrap conditions, special care needs to be given for limiting the ac peak current plus the dc current to 2A as shown in Table 7-3.

Table 7-3 Total Current from AC and DC Loads
Output Voltage (VPP) Resistive Load (Ω) DC Current (mA) Capacitive Load (pF) Max Slew Rate (V/μs) AC Peak Current (mA) AC + DC Peak Current (mA)
±40 Open 0 300 2000 600 600
±40 Open 0 1000 2000 2000 2000
±50 Open 0 300 2000 600 600
±50 Open 0 1000 2000 2000 2000
±40 100 ±400 300 2000 600 1000
±40 100 ±400 1000 1600 1600 2000
±50 100 ±500 300 2000 600 1100
±50 100 ±500 1000 1500 1500 2000

While the bootstrap design provides some benefits, such as 100V output range with a 60V amplifier, there are some design considerations to understand about the architecture. One of the key drawbacks to this design is that the output headroom limitations are doubled to 6V from each rail due to the supply amplifier and the signal amplifier both being limited to 3V (no load) from the individual supplies. In addition, the output headroom of each amplifier increases as the device is heated up and provides more current from the output. For this reason, the 120V supply loses about 20V of headroom (10V from VEE and 10V from VCC) under heavy load conditions. Designers must pay attention to Figure 5-33 for information about headroom loss, and estimate the worst-case junction temperature of each amplifier for the application.

When driving these heavy loads, designers must pay special attention to the max junction temperature of the device (150C) and keep the device within the safe operating area, as shown in Section 7.5.1.2. A benefit of the bootstrap design, compared to a single 120V amplifier, is that the design splits the power consumed on the die between the signal amplifier and the supply amplifiers as shown in Figure 7-6. A traditional 120V amplifier typically consumes 30W of power in this same scenario, since the 30V of drop must occur on one output stage transistor, whereas the bootstrap design splits the 30W of power between the signal and supply amplifier. Since the THS3470 package can optimistically source 4°C/W, this means the bootstrap can increase the total power consumed from 30W to 60W at an ambient temperate of 25C.

Note: 4°C/W for Theta JA performance is a best case high airflow scenario that requires considerable design considerations. For more information about practical thermal performance, see Section 7.5.1.
Note: The thermal pad of the THS3470 is internally connected to VEE on the device. Designers need to create electrical isolation between the different amplifier's thermal pads of the bootstrap design, since the VEE pins are all biased to different voltages. See Section 7.5.1.1 for more information about electrical isolation and thermal performance.

When using the digital features of the THS3470, the DGND of the signal amplifier must be connected to the VEE pin instead of board ground, otherwise the digital blocks of the THS3470 can exceed the supply range of the device while the output signal is moving. Likewise, for the VEE supply amplifier, the DGND range can only operate 7V from the positive supply (0V in this design). Because of this, many of the digital pins (P0, P1, OVTEMP_FLAG, ISNK_FLAG, ISRC_FLAG, ISNK_LIMIT_EN, ISRC_LIMIT_EN) for the THS3470 must be connected with respect to DGND and VDD to prevent device damage. Reading the status of a flag for the signal amplifier during fast transients requires level shifting circuits (difference amplifier), so designers can use the device flags on the supply amplifiers with current limits disabled to limit the complexity of the circuit.

To set a current limit with the bootstrap circuit, set the signal amplifier current limit to the desired value, using a resistor to connect ISRC_LIMIT to VEE and ISNK_LIMIT to VCC, and leave the supply amplifier current limits at the maximum (1.35A DC). If the supply amplifiers enter into current limit before the signal amplifier, the signal amplifier can experience damage. The IOUT_MONITOR pin is not suggested to be used on the signal amplifier, because the VMID voltage is moving with the output voltage. IOUT_MONITOR can be monitored on the supply amplifiers if current monitoring is desired on the bootstrap design.

THS3470 THS3470 Bootstrap PCB Figure 7-7 THS3470 Bootstrap PCB