SBOSA39A April   2025  – October 2025 THS3470

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics ±VS = ±30V
    6. 5.6 Electrical Characteristics ±VS = ±20V
    7. 5.7 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Output Current Limit
      2. 6.3.2 Output Current Enable
      3. 6.3.3 Over Temperature Flag
      4. 6.3.4 Output Current Flags
      5. 6.3.5 Output Current Monitoring
      6. 6.3.6 Die Temperature Monitoring
      7. 6.3.7 External Compensation
    4. 6.4 Device Functional Modes
      1. 6.4.1 Power Modes
      2. 6.4.2 Choosing a Feedback Resistor
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 High-Voltage, High-Precision, Composite Amplifier
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
      2. 7.2.2 120V Bootstrap Amplifier
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
        3. 7.2.2.3 Application Performance Plots
    3. 7.3 Short Circuit Protection
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Thermal Considerations
        1. 7.5.1.1 Top-Side Cooling Benefits
        2. 7.5.1.2 THS3470 Safe Operating Area
      2. 7.5.2 Layout Guidelines
      3. 7.5.3 Layout Example
  9. Device and Documentation Support
    1. 8.1 Documentation Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 TAPE AND REEL INFORMATION

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • REB|42
Thermal pad, mechanical data (Package|Pins)
Orderable Information

THS3470 Safe Operating Area

The Safe Operating Area of a device helps designers to identify best practices for managing inherent power limitations of semiconductor devices. For operational amplifiers, these limitations typically manifest through large output currents paired with large voltage drop across the output transistors. The high voltage and high current nature of the THS3470 inherently dissipates more power inside the package, thus special design considerations must be taken to optimize device health over lifetime. For more information regarding sources of stress for power amplifiers with regards to the Safe Operating Area, see SBOA022.

The THS3470 is equipped with a top-side cooled REB package, which helps to optimize thermal performance when burning large amounts of power inside the package. For DC, or near DC performance (i.e. high duty cycle and/or >100ms pulses), power burned in the output stage causes the device to heat up at a near worst-case scenario. While the THS3470 does include diagnostic and protection features such as the DIE_TEMP and OVERTEMP_FLAG to help with thermal management, best practice for enabling device integrity includes planning for the safe operating area of the device.

Figure 7-17 shows how the THS3470 functions at different output voltages and output currents under different cooling conditions. These results showcase the necessity of a heat sink in most applications, with a nearly 2x improvement in power delivered by adding the heat sink. Additionally, the convection across the heat sink fins is the primary mechanism for removing the heat from the die. Figure 7-17 shows 3 scenarios that highlight air flow and heat sink impact: no heat sink, heat sink without air flow (THS3470EVM without fan), and heat sink with air flow (THS3470EVM with fan).

THS3470 THS3470 DC Safe Operating Area
                    (THS3470EVM, VS = 60V) Figure 7-17 THS3470 DC Safe Operating Area (THS3470EVM, VS = 60V)
Note: Thermal performance of the THS3470 is only shown at the worst case (60V) for the device. Using the device at lower supply voltage reduces the power consumed in the package and results in better thermal performance.

In addition to dc operation, the THS3470's high slew rate and bandwidth make the device well suited for large voltage pulses. Many applications for the THS3470 use low duty cycle pulses to minimize power dissipated in the system, instead of using a continuous dc voltage, which is often characterized by an "IV Chart". Figure 7-18 shows how the thermal performance of the THS3470 changes under various pulse durations and duty cycles with a purely resistive load while using the THS3470EVM, heat sink, and fan.

THS3470 THS3470 Safe Operating Area
                    (Square Wave, VS = 60V) Figure 7-18 THS3470 Safe Operating Area (Square Wave, VS = 60V)

When driving capacitive loads, Figure 7-19 shows how the THS3470 power consumption changes versus frequency for a square wave with a fixed capacitive load. Since the current into a capacitor is directly correlated to the dv/dt of the output step multiplied by the capacitance, all of the power consumption occurs during the slew event of the square wave. Higher frequencies contain more edges within the same time span, so the THS3470 consumes more power and generates more heat as the frequency increases while driving capacitive loads. The effect of different capacitive loads for a fixed voltage can also be seen in Figure 7-20.

THS3470 THS3470 Safe Operating Area
                    (Square Wave, CL = 1nF, VS = 60V) Figure 7-19 THS3470 Safe Operating Area (Square Wave, CL = 1nF, VS = 60V)
THS3470 THS3470 Safe Operating Area
                    (Square Wave, VOUT = 50VPP, VS = 60V) Figure 7-20 THS3470 Safe Operating Area (Square Wave, VOUT = 50VPP, VS = 60V)
Note: The input slew rate is configured to limit the peak current to 2A for various capacitive loads in Figure 7-20.