SLUSCC7C July 2016 – June 2018 TPS546C23
This bit allows bypassing the normal valid data checks on register writes. This feature is included for flexibility during debug to quickly generate fault conditions and/or possibly work around any data limit protection mechanisms prohibiting output voltage programming. This bit does not have EEPROM backup.
|0||Normal PMBus data write restrictions|
|1||Data write restrictions are overridden for the following registers: SMBALERT_MASK, VOUT_COMMAND, VOUT_SCALE_LOOP, VREF_TRIM, STEP_VREF_MARGIN_HIGH, STEP_VREF_MARGIN_LOW, IOUT_OC_FAULT_LIMIT, IOUT_OC_WARN_LIMIT, OT_FAULT_LIMIT, OT_WARN_LIMIT, VOUT_MIN, VOUT_MAX, VIN_ON, VIN_OFF, and OPERATION.|
CAUTION: Users should use this bit with extreme caution. Setting this bit allows invalid data conditions to be programmed into the device which can lead to damage. Invalid data written into any register when DLO is enabled does NOT set the IVD bit; nor trigger SMBALERT. The invalid data is simply allowed to be programmed. Furthermore, invalid data programmed into a command/status register while DLO is enabled, does not trigger SMBALERT upon deassertion of DLO. So, it is possible to exit DLO mode with invalid data in command/status registers. Use with extreme caution.