SLUSCC7C July 2016 – June 2018 TPS546C23
The SW pin connects to the switching node of the power-conversion stage and acts as the return path for the high-side gate driver. When configured as a synchronous buck stage, the voltage swing on SW normally traverses from below ground to well above the input voltage. Parasitic inductance in the high-side FET and the output capacitance (COSS) of both power FETs form a resonant circuit that can produce high frequency ( > 100 MHz) ringing on this node. The voltage peak of this ringing, if not controlled, can be significantly higher than the input voltage. Ensure that the peak ringing amplitude does not exceed the absolute maximum rating limit for the pin.
In many cases, a series resistor and capacitor snubber network connected from the switching node to PGND can be helpful in damping the ringing and decreasing the peak amplitude. Provide provisions for snubber network components in the layout of the printed circuit board. If testing reveals that the ringing amplitude at the SW pin exceeds the limit, then include snubber components. For more information about snubber circuits design, refer to Snubber Circuits: Theory, Design and Application (SLUP100).
Placing a BOOT resistor in series with the BOOT capacitor slows down the turnon of the high-side FET and can help to reduce the peak ringing at the switching node as well.