SLUSCC7C July 2016 – June 2018 TPS546C23
Without power cycling, the VOUT_COMMAND value and the corresponding output voltage can be reset to the default value which is latched when the devices are powered up from AVIN. When the RESET/PGD pin is pulled low, the digital core sets the VOUT_COMMAND value to the default value. Figure 26 shows the timing diagram for resetting the output voltage. When theRESET/PGD pin is asserted low, after a short delay (less than 2 µs), the output voltage begins to transition from the current value to the default VOUT_COMMAND value according to the slew-rate set in the VOUT_TRANSITION_RATE command. The VOUT_COMMAND value does not change to any values programmed in the VOUT_COMMAND register while the RESET/PGD pin is held low. The reset_vout status bit in the STATUS_MFR_SPECIFIC (80h) register is set for indication.
In the case of fault restart, the user has access to allow the VOUT_COMMAND value to be reset to the initial boot-up voltage by setting the RST_VOUT_oSD Bit in the OPTIONS (MFR_SPECIFIC_21) (E5h) register.