SLUSCC7C July 2016 – June 2018 TPS546C23
The device supports auto detection on the SYNC pin of the stand-alone device or the PWM-loop master device in a 2-phase configuration. With the external clock applied to the SYNC pin before AVIN power-up or pulling up the SYNC pin to the BP3 or BP6 pin, the SYNC pin is configured as SYNC-IN, and is synchronized to the rising edge of the external clock applied to this pin, with a minimum pulse width of 200 ns (maximum). If no external clock edges occur or logic-high voltage is applied to the SYNC pin at AVIN power-up, the SYNC pin is configured as SYNC-OUT, and the internal free-running frequency set by the RT resistor is output on the SYNC pin. A sudden change in synchronization clock frequency causes an associated control-loop response, resulting in an overshoot or undershoot on the output voltage.