SLUSCC7C July 2016 – June 2018 TPS546C23
The converter is allowed to stop switching after detecting the SYNC signal is expected, but not present or has been lost. The device also reports a live (essentially unlatched) sync_flt bit in the STATUS_MFR_SPECIFIC (80h) register. The SMBALERT is not triggered if the SYNC_FAULT bit goes high. The default SYNC fault response is as follows.
The SYNC fault response can be disabled by setting the SYNC_FAULT_DIS Bit in the MISC_CONFIG_OPTIONS (MFR_SPECIFIC_32) (F0h) register. The SYNC_FAULT_DIS Bit, when set, disables the sync_flt reporting status, and the devices that lost the SYNC clock input (loop slave or loop master set clock slave) continue to operate at a frequency approximately 40% less than the free-running frequency for approximately 10 µs, then back to the free-running frequency without shutting down. But the frequencies of two devices are most likely not identical because the clock master continues to operate at its own free-running frequency.