10.1 Layout Guidelines
Layout is critical for good power-supply design. Figure 52 shows the recommended PCB-layout configuration. A list of PCB layout considerations using these devices is listed as follows:
- As with any switching regulator, several power or signal paths exist that conduct fast switching voltages or currents. Minimize the loop area formed by these paths and their bypass connections.
- Bypass the PVIN pins to PGND with a low-impedance path. The input bypass capacitors of the power-stage should be placed as close as physically possible to the PVIN and PGND pins. Additionally, a high-frequency bypass capacitor in a 0402 package on the PVIN pins can help reduce switching spikes. This capacitor which can be placed on the other side of the PCB directly underneath the device to keep a minimum loop.
- The BP6 bypass capacitor carries a large switching current for the gate driver. Bypassing the BP6 pin to PGND with a low-impedance path is very critical to the stable operation of the devices. Place the BP6 high-frequency bypass capacitors as close as possible to the device pins, with a minimum return loop back to ground.
- The AVIN and BP3 pins also require good local bypassing. Place bypass capacitors as close as possible to the device pins, with a minimum return loop back to ground. This return loop should be kept away from fast switching voltages, the main current path, and the BP6 current path. Poor bypassing on the AVIN and BP3 pins can degrade the performance of the device.
- Keep signal components local to the device, and place them as close as possible to the pins to which they are connected. These components include the feedback resistors and the RT resistor. These components should also be kept away from fast switching voltage and current paths. Those components can be terminated to AGND with a minimum return loop or bypassed to the copper area of a separate low-impedance analog ground (AGND) that is isolated from fast switching voltages and current paths and has single connection to PGND on the thermal pad through the AGND pin. For placement recommendations, see Figure 52.
- The PGND pin (pin 26) must be directly connected to the thermal pad of the device on the PCB, with a low-noise, low-impedance path to ensure accurate current monitoring.
- Minimize the SW copper area for best noise performance. Route sensitive traces away from the SW and BOOT pins as these nets contain fast switching voltages and lend easily to capacitive coupling.
- Snubber component placement is critical for effective ringing reduction. These components should be on the same layer as the devices, and be kept as close as possible to the SW and PGND copper areas.
- The PVIN and AVIN pins must be the same potential for accurate short circuit protection, but high-frequency switching noise on the AVIN pin can degrade performance. The AVIN pin should be connected to PVIN through a trace from the input copper area. Optionally form a small low-pass R-C between the PVIN and AVIN pins, with the AVIN bypass capacitor (1 µF) and a 0-2 Ω resistor between the PVIN and AVIN pins. See Figure 52 for placement recommendations.
- Route the RSP and RSN lines from the output capacitor bank at the load back to the device pins as a tightly coupled differential pair. These traces must be kept away from switching or noisy areas which can add differential-mode noise.
- Use caution when routing of the SYNC, VSHARE and ISHARE traces for 2-phase configurations. The SYNC trace carries a rail-to-rail signal and should be routed away from sensitive analog signals, including the VSHARE, ISHARE, RT, and FB signals. The VSHARE and ISHARE traces should also be kept away from fast switching voltages or currents formed by the PVIN, AVIN, SW, BOOT, BP6 pins.