SLUSCC7C July 2016 – June 2018 TPS546C23
These bits set the overcurrent fault response to either ignore or not. The default for this bit is 11b. Any value other than 00b or 11b will not be accepted, such and attempt will cause the ’cml’ bit in the STATUS_BYTE register and the ivd bit in the STATUS_CML register to be set, and assert SMBALERT. Because both bits must be the same, only one (bit 7) is stored in EEPROM. The default for this bit is 11b.
|00||The PMBus device continues operation without interruption. Note: In this “ignore” fault response mode, the associated fault status bits are set. Additionally, SMBALERT continues to be triggered if it is not masked.|
|11||The PMBus device shuts down and restarts according to RS[2:0].|