The TPS65214 offers various fault-detections. Per default, all of them lead to a sequenced shut-down. Some of them are maskable and the reaction to masked faults is configurable.

Supply Voltage Monitoring

The device provides the following fault-detections on the supply voltage (VSYS) and internal voltage supply (VDD1P8). None of these faults are maskable.

• Undervoltage on VSYS, resulting in transition to OFF state or gating start-up
• Overvoltage-protection on VSYS, resulting in transition to OFF state
• Under- or Overvoltage on internal 1.8V-supply (VDD1P8), resulting in transition to OFF state or gating start-up.

Regulator Output Monitoring

The TPS65214 provides the following fault-detections on the buck- and LDO-outputs:

• Undervoltage detection (UV)
• Over Current detection (OC), triggering on positive as well as (for buck-converters) negative current-limit
• Short-to-GND detection (SCG)
• Temperature warning (WARM) and Thermal Shut Down (TSD / HOT)
• Residual Voltage (RV) and Residual Voltage - Shutdown (RV_SD)
• Timeout (TO)

SCG, OC, HOT, and TO are not maskable. If any one of those occurs, the device powers down. Positive and negative current limit share the same mask-bit per regulator.

The reaction to UV, RV and WARM faults is configurable. If not masked, a fault triggers a sequenced shut-down. UV, RV and WARM can be masked individually per regulator in INT_MASK_BUCKS, INT_MASK_LDOS and INT_MASK_WARM registers. No state-transition occurs in case of a masked fault. Whether bits are set and if nINT is pulled low can be configured globally by MASK_EFFECT bits in MASK_CONFIG register. Positive and negative current limit share the same mask-bit per regulator.

• 00b = no state change, no nINT reaction, no bit set
• 01b = no state change, no nINT reaction, bit set
• 10b = no state change, nINT reaction, bit set (same as 11b)
• 11b = no state change, nINT reaction, bit set (same as 10b)

For any fault that corresponds to a shut-down condition, the fault-bit remains asserted until a W1C (write-one-clear) operation is performed via I2C (assuming the fault is not present any more). In case of a shut-down fault, no renewed on-request is required. The device automatically executes the power up sequence if the fault is no longer present as long as EN/VSENSE is still high and no PB-press is required for a restart.

For any fault that is not a shut-down condition (for example because the fault is masked), the bit is cleared when going to the INITIALIZE state.

Thermal Warning and Shutdown

There are two thermal thresholds: Thermal-warning (WARM) and Thermal Shutdown (TSD / HOT).

Thermal Warning, WARM-threshold

If the temperature exceeds T_{WARM_Rising} threshold, the SENSOR_x_WARM-bit is set and the PMIC sequences down (unless masked). When the temperature fell below T_{WARM_Falling} threshold, the device powers up again, without a new
 Push-button-ON_Request. In EN or VSENSE configuration, the ON-request must still be valid to transition to ACTIVE state.

If the temperature exceeds T_{WARM_Rising} threshold, but SENSOR_x_WARM_MASK bit is /bits are set, the PMIC remains in ACTIVE state. Fault-reporting occurs as configured by MASK_EFFECT bits. The processor makes the decision to either sequence the power down or throttles back on the running applications to reduce the power consumption and hopefully avoiding a Thermal Shutdown situation.

Thermal Shutdown, HOT-threshold

If the temperature exceeds T_{HOT_Rising} threshold, the SENSOR_x_HOT-bit is set and the PMIC powers off all rails immediately. This power down is simultaneously and not sequenced.

• If ALL sensors are masked for WARM-detection (all SENSOR_x_WARM_MASK bits are set), the PMIC does power back up once the temperature drops below the T_{HOT_Falling} threshold, provided a valid ON-request is present.
• If any one of the sensors is unmasked for WARM-detection, the PMIC does power back up once the temperature drops below the T_{WARM_Falling} threshold, without a new
 Push-button-ON_Request. In EN or VSENSE configuration, the ON-request must still be valid to transition to ACTIVE state.

Residual Voltage

Residual voltage checks are performed for each power rail before the rail is enabled, regardless if during the sequence or by I2C-command. The treatment of RV-faults depends on the situation when the fault occurs. A simplified state diagram to illustrate residual voltage checking is shown in Figure 7-16.

Figure 7-16 Residual Voltage Checking

1. In the case of residual voltage when sequencing up, the device sets the respective INT_TIMEOUT_RV_SD_IS_SET bit in INT_SOURCE register, LDOx_RV_SD respectively BUCKx_RV_SD bit and bit TIMEOUT in INT_TIMEOUT_RV_SD register, and initiates the power-down sequence at the end of the slot.

2. In case of residual voltage when sequencing down to the STBY or SLEEP state, the device gates the power-down of subsequent rails for up to eight times the power-down slot duration. If the residual voltage is still present, the device sets the following bits and initiates the power-down sequence.
   1. Bit INT_TIMEOUT_RV_SD_IS_SET in register INT_SOURCE
   2. Respective bit LDOx_RV_SD or BUCKx_RV_SD in register INT_TIMEOUT_RV_SD
   3. Bit TIMEOUT in register INT_TIMEOUT_RV_SD
3. In case of residual voltage when sequencing down to the INITIALIZE state, no status bits are set, and the power-down sequence continues after eight times the power-down slot-duration.

4. In case of residual voltage during the power-up or power-down of a rail via I2C command, the device sets the respective LDOx_RV or BUCKx_RV bit. If the MASK_INT_FOR_RV bit is not set (RV is unmasked), the device pulls the nINT pin low.

The shutdown-fault-reaction in case of residual voltage detection when sequencing up or down is maskable by the BYPASS_RV_FOR_RAIL_ENABLE bit in the GENERAL_CONFIG register. The reaction of the nINT pin in case of residual voltage detection by I2C command is maskable by the MASK_INT_FOR_RV bit in the MASK_CONFIG register.

A timeout occurs if the residual voltage cannot be discharged after the power-up slot-duration, or after eight times the power-down slot-duration. The device sets the TIMEOUT bit in the INT_TIMEOUT_RV_SD register.

Retry Counter

For every detected Shut-Down fault, the retry counter (RETRY_COUNT in POWER_UP_STATUS_REG register) is incremented. The device attempts two retries to power-up. If both fail, a power-cycle on VSYS is required to reset the retry counter. Any successful power-up also resets the retry counter. Masked faults do not cause a shut-down and do not increment the retry counter.

The retry counter can be deactivated on first power up via the MASK_RETRY_COUNT_ON_FIRST_PU bit in the MFP_2_CONFIG register. When set, the device retries infinitely until the first power-up sequence is completed.

The retry counter can also be deactivated permanently by the MASK_RETRY_COUNT bit in the INT_MASK_UV register. When set, the device retries infinitely following any shut-down fault.

Fault Reaction Overview

Below table gives an overview of the fault-behavior in ACTIVE and STBY states if unmasked and whether a fault is maskable.