SLVSHK7A March   2025  – December 2025 TPS65214

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  System Control Thresholds
    6. 6.6  BUCK1, BUCK2, BUCK3 Converter
    7. 6.7  General Purpose LDOs (LDO1, LDO2)
    8. 6.8  GPIOs and multi-function pins (EN/PB/VSENSE, nRSTOUT, nINT, GPO/nWAKEUP, GPIO/VSEL, MODE/STBY)
    9. 6.9  Voltage and Temperature Monitors
    10. 6.10 I2C Interface
    11. 6.11 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power-Up Sequencing
      2. 7.3.2  Power-Down Sequencing
      3. 7.3.3  Push Button and Enable Input (EN/PB/VSENSE)
      4. 7.3.4  OFF-Request by I2C Command
      5. 7.3.5  First Supply Detection (FSD)
      6. 7.3.6  Input Voltage Slew Rate With Automatic Power-up
      7. 7.3.7  Buck Converters (Buck1, Buck2, and Buck3)
      8. 7.3.8  Linear Regulators (LDO1 and LDO2)
      9. 7.3.9  Reset to SoC (nRSTOUT)
      10. 7.3.10 Interrupt Pin (nINT)
      11. 7.3.11 PWM/PFM and Low Power Modes (MODE/STBY)
      12. 7.3.12 General Purpose Input/Output and Voltage Select Pin (GPIO/VSEL)
      13. 7.3.13 General Purpose Output and nWAKEUP (GPO/nWAKEUP)
      14. 7.3.14 RESET-Request by I2C Command
      15. 7.3.15 Register Access Control
      16. 7.3.16 I2C-Compatible Interface
        1. 7.3.16.1 Data Validity
        2. 7.3.16.2 Start and Stop Conditions
        3. 7.3.16.3 Transferring Data
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
        1. 7.4.1.1 OFF State
        2. 7.4.1.2 INITIALIZE State
        3. 7.4.1.3 ACTIVE State
        4. 7.4.1.4 STBY State
        5. 7.4.1.5 SLEEP State
        6.       49
        7. 7.4.1.6 Fault Handling
  9. 8 User Registers
    1. 8.1 Device Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Typical Application Example
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
        1. 9.2.3.1 Application Curves
        2. 9.2.3.2 Buck1, Buck2, Buck3 Design Procedure
        3. 9.2.3.3 LDO1, LDO2 Design Procedure
        4. 9.2.3.4 VSYS, VDD1P8
        5. 9.2.3.5 Digital Signals Design Procedure
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

7.4.1.5 SLEEP State

SLEEP state is an ultra-low-power mode of operation intended to minimize power consumption. After setting the STBY_SLEEP_CONFIG bit, SLEEP mode can be entered by the MODE/STBY pin, if configured as 'STBY' or by an I2C-command to STBY_I2C_CTRL in MFP_CTRL register. All power rails and most functional blocks, including all monitors, are turned off in this state. The only active I/Os is EN/PB/VSENSE, which must be configured as EN or PB to transition from SLEEP directly to INITIALIZE. If EN/PB/VSENSE is configured as VSENSE, the device can only exit the SLEEP state by going to the OFF state.

When EN/PB/VSENSE is configured as EN or PB via 'EN_PB_VSENSE_CONFIG', the device transitions from the SLEEP state to the INITIALIZE state upon detection of EN rising edge or PB falling edge and associated deglitch (tDEGL_ANALOG_EN followed by tOFF_TO_INIT). The PMIC reads the NVM contents and loads the NVM-default values to the registers. The PMIC then waits for tEN_PB_WAKEUP and associated deglitch to elapse. After the timer elapses, the POWER_UP_FROM_EN_PB_VSENSE bit in POWER_UP_STATUS_REG register is set, the device transitions to the ACTIVE state, and begins the power-up sequence if no other faults are present. If the state of the EN/PB/VSENSE pin changes and surpasses the associated deglitch (tDEGL_EN_RISE_Fall or tDEGL_PB_RISE) before tEN_PB_WAKEUP elapses, a PB_EN_SLEEP_EXIT_TIMEOUT is detected, and the device transitions back to the SLEEP state.

The sequence into SLEEP state is the same as the power-down sequence. See Figure 7-15 for more details.

CAUTION: The device can only transition to the SLEEP state from the ACTIVE state (via 'STBY' or STBY_I2C_CTRL) or from the INITIALIZE state (via SLEEP_EXIT_TIMEOUT).
CAUTION: The 'EN_PB_VSENSE_CONFIG' setting can be changed during operation. For wakeup detection, the device refers to the 'EN_PB_VSENSE_CONFIG' setting when the SLEEP state is entered.
CAUTION: Do not change the registers related to an ongoing sequence by I2C-command!

Non-NVM-bits are not accessible for approximately 80us after starting a transition into INITIALIZE state.