SLVSHK7A March   2025  – December 2025 TPS65214

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  System Control Thresholds
    6. 6.6  BUCK1, BUCK2, BUCK3 Converter
    7. 6.7  General Purpose LDOs (LDO1, LDO2)
    8. 6.8  GPIOs and multi-function pins (EN/PB/VSENSE, nRSTOUT, nINT, GPO/nWAKEUP, GPIO/VSEL, MODE/STBY)
    9. 6.9  Voltage and Temperature Monitors
    10. 6.10 I2C Interface
    11. 6.11 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power-Up Sequencing
      2. 7.3.2  Power-Down Sequencing
      3. 7.3.3  Push Button and Enable Input (EN/PB/VSENSE)
      4. 7.3.4  OFF-Request by I2C Command
      5. 7.3.5  First Supply Detection (FSD)
      6. 7.3.6  Input Voltage Slew Rate With Automatic Power-up
      7. 7.3.7  Buck Converters (Buck1, Buck2, and Buck3)
      8. 7.3.8  Linear Regulators (LDO1 and LDO2)
      9. 7.3.9  Reset to SoC (nRSTOUT)
      10. 7.3.10 Interrupt Pin (nINT)
      11. 7.3.11 PWM/PFM and Low Power Modes (MODE/STBY)
      12. 7.3.12 General Purpose Input/Output and Voltage Select Pin (GPIO/VSEL)
      13. 7.3.13 General Purpose Output and nWAKEUP (GPO/nWAKEUP)
      14. 7.3.14 RESET-Request by I2C Command
      15. 7.3.15 Register Access Control
      16. 7.3.16 I2C-Compatible Interface
        1. 7.3.16.1 Data Validity
        2. 7.3.16.2 Start and Stop Conditions
        3. 7.3.16.3 Transferring Data
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
        1. 7.4.1.1 OFF State
        2. 7.4.1.2 INITIALIZE State
        3. 7.4.1.3 ACTIVE State
        4. 7.4.1.4 STBY State
        5. 7.4.1.5 SLEEP State
        6.       49
        7. 7.4.1.6 Fault Handling
  9. 8 User Registers
    1. 8.1 Device Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Typical Application Example
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
        1. 9.2.3.1 Application Curves
        2. 9.2.3.2 Buck1, Buck2, Buck3 Design Procedure
        3. 9.2.3.3 LDO1, LDO2 Design Procedure
        4. 9.2.3.4 VSYS, VDD1P8
        5. 9.2.3.5 Digital Signals Design Procedure
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

6.5 System Control Thresholds

Over operating free-air temperature range (unless otherwise noted). Specified voltage levels are in reference to the AGND ground of the device.
POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Electrical Characteristics
4.1.1 VSYS Operating Input Voltage 2.5 5.5 V
4.1.2 VSYSUVLO_Rising VSYS UVLO rising threshold Measured on VSYS pin, untrimmed 2.2 2.5 V
4.1.2.2 VSYSPOR_Rising VSYS POR rising threshold Measured on VSYS pin, untrimmed 1.8 2.275 V
4.1.3 VSYSUVLO_Falling VSYS UVLO falling threshold Measured on VSYS pin, trimmed 2.175 2.25 V
4.1.3.2 VSYSPOR_Falling VSYS POR falling threshold Measured on VSYS pin, trimmed 1.6 2.15 V
4.1.4 VSYSUVLO_Hyst VSYS UVLO hysteresis VSYSUVLO_Rising_untrimmed-VSYSUVLO_Falling_trimmed 130 mV
4.1.5 VVSYS_OVP_Rise VSYS OVP rising threshold, trimmed Measured on VSYS pin, trimmed 5.8 6.1 V
4.1.6 VVSYS_OVP_Fall VSYS OVP falling threshold, trimmed Measured on VSYS pin, trimmed 5.7 5.95 V
4.1.7 VVSYS_OVP_Hyst VSYS OVP hysteresis VSYSOVP_Rising_trimmed-VSYSOVP_falling_trimmed 100 140 180 mV
4.1.8 VVDD1P8 VDD1P8 voltage 1.7 1.8 1.9 V
4.2.1a IINITIALIZE Current Consumption in INITIALIZE state Combined Current from VSYS and PVIN_x pins. VSYS = PVIN_Bx = PVIN_LDOx = 3.6V. All Monitors are off.
TA = 25°C		 13 20 µA
4.2.1b IINITIALIZE Current Consumption in INITIALIZE state Combined Current from VSYS and PVIN_x pins. VSYS = PVIN_Bx = PVIN_LDOx = 3.6V. All Monitors are off.
TA = -40°C to 105°C		 13 30 µA
4.2.2a IACTIVE ACTIVE State Current Consumption, all rails on Combined Current from VSYS and PVIN_x pins. VSYS = PVIN_Bx = PVIN_LDOx = 3.6V. All Outputs are on, all LDOs in LDO-mode, Bucks in PFM mode. No Load.
TA = 25°C		 230 270 µA
4.2.2b IACTIVE ACTIVE State Current Consumption, all rails on Combined Current from VSYS and PVIN_x pins. VSYS = PVIN_Bx = PVIN_LDOx = 3.6V. All Outputs are on, all LDOs in LDO-mode, Bucks in PFM mode. No Load.
TA = -40°C to 105°C		 230 310 µA
4.2.3a ISTBY STBY State Current Consumption, BUCK2, BUCK3, and LDO2 on Combined Current from VSYS and PVIN_x pins. VSYS = PVIN_Bx = PVIN_LDOx = 3.6V. BUCK2, BUCK3, and LDO2 on in LDO-mode, Bucks in PFM mode. No Load.
TA = 25°C		 130 155 µA
4.2.3b ISTBY STBY State Current Consumption, BUCK2, BUCK3, and LDO2 on Combined Current from VSYS and PVIN_x pins. VSYS = PVIN_Bx = PVIN_LDOx = 3.6V. BUCK2, BUCK3, and LDO2 on in LDO-mode, Bucks in PFM mode. No Load.
TA = -40°C to 105°C		 155 170 µA
4.2.4a ISTBY STBY State Current Consumption, all rails on Combined Current from VSYS and PVIN_x pins. VSYS = PVIN_Bx = PVIN_LDOx = 3.6V. All Outputs are on, all LDOs in LDO-mode, Bucks in PFM mode. No Load.
TA = 25°C		 230 270 µA
4.2.4b ISTBY STBY State Current Consumption, all rails on Combined Current from VSYS and PVIN_x pins. VSYS = PVIN_Bx = PVIN_LDOx = 3.6V. All Outputs are on, all LDOs in LDO-mo, Bucks in PFM mode. No Load.
TA = -40°C to 105°C		 230 310 µA
4.2.6a ISLEEP SLEEP State Current Consumption Combined Current from VSYS and PVIN_x pins. VSYS = PVIN_Bx = PVIN_LDOx = 3.6V. Most blocks off.
TA = 25°C		 3 5 µA
4.2.6b ISLEEP SLEEP State Current Consumption Combined Current from VSYS and PVIN_x pins. VSYS = PVIN_Bx = PVIN_LDOx = 3.6V. Most blocks off.
TA = -40°C to 105°C		 3 15 µA
Timing Requirements
4.3.1 tOFF_TO_INIT Time from VSYS passing VSYS_UVLO until entering INITIALIZE state, including NVM-read, ready for ON-request Time from VSYS passing VSYS_UVLO until entering INITIALIZE state. On request execution gated by HOT 6.2 ms
4.3.2a tTIMEOUT_UV_BUCK UV-detection in case a Buck rail does not reach UV-threshold during ramp-up 1.8 ms
4.3.2b tTIMEOUT_UV_LDO UV-detection in case a LDO rail does not reach UV-threshold during ramp-up 1.4 ms
4.3.3 tON_DLY Time from valid ON-request received to the first sequence slot All buck outputs below VBUCKx_SCG_TH. All LDO outputs below VLDOx_SCG_TH.  280 µs
4.10.7b tNVM_LOAD Time from VDD1P8 > VDD1P8_POR until entering INITIALIZE state, ready for ON-request 4.95 ms