SLVSHK7A March   2025  – December 2025 TPS65214

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  System Control Thresholds
    6. 6.6  BUCK1, BUCK2, BUCK3 Converter
    7. 6.7  General Purpose LDOs (LDO1, LDO2)
    8. 6.8  GPIOs and multi-function pins (EN/PB/VSENSE, nRSTOUT, nINT, GPO/nWAKEUP, GPIO/VSEL, MODE/STBY)
    9. 6.9  Voltage and Temperature Monitors
    10. 6.10 I2C Interface
    11. 6.11 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power-Up Sequencing
      2. 7.3.2  Power-Down Sequencing
      3. 7.3.3  Push Button and Enable Input (EN/PB/VSENSE)
      4. 7.3.4  OFF-Request by I2C Command
      5. 7.3.5  First Supply Detection (FSD)
      6. 7.3.6  Input Voltage Slew Rate With Automatic Power-up
      7. 7.3.7  Buck Converters (Buck1, Buck2, and Buck3)
      8. 7.3.8  Linear Regulators (LDO1 and LDO2)
      9. 7.3.9  Reset to SoC (nRSTOUT)
      10. 7.3.10 Interrupt Pin (nINT)
      11. 7.3.11 PWM/PFM and Low Power Modes (MODE/STBY)
      12. 7.3.12 General Purpose Input/Output and Voltage Select Pin (GPIO/VSEL)
      13. 7.3.13 General Purpose Output and nWAKEUP (GPO/nWAKEUP)
      14. 7.3.14 RESET-Request by I2C Command
      15. 7.3.15 Register Access Control
      16. 7.3.16 I2C-Compatible Interface
        1. 7.3.16.1 Data Validity
        2. 7.3.16.2 Start and Stop Conditions
        3. 7.3.16.3 Transferring Data
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
        1. 7.4.1.1 OFF State
        2. 7.4.1.2 INITIALIZE State
        3. 7.4.1.3 ACTIVE State
        4. 7.4.1.4 STBY State
        5. 7.4.1.5 SLEEP State
        6.       49
        7. 7.4.1.6 Fault Handling
  9. 8 User Registers
    1. 8.1 Device Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Typical Application Example
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
        1. 9.2.3.1 Application Curves
        2. 9.2.3.2 Buck1, Buck2, Buck3 Design Procedure
        3. 9.2.3.3 LDO1, LDO2 Design Procedure
        4. 9.2.3.4 VSYS, VDD1P8
        5. 9.2.3.5 Digital Signals Design Procedure
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

9.2.3.5 Digital Signals Design Procedure

This section describes the external connections required for the digital pins. A VIO supply of 3.3V or 1.8V is commonly used as the voltage level for the digital signals that require an external pull-up. However, higher voltage can be used (up to the maximum spec). The VIO supply for the digital pins on the PMIC must be the same as the IO domain for the digital signal that is connected to on the processor. 100kΩ is the recommended pull-up resistor for EN/PB/VSENSE. Pull-up resistor for I2C pins can be calculated based on system requirements. All other digital pins can use 10kΩ.

If GPO or GPIO is assigned to the first slot of the power-up sequence to enable an external discrete, they can be pulled up to VSYS.

The EN/PB/VSENSE pin can be driven externally to enable the PMIC. However, if the application does not have an external signal dedicated to drive this pin, it can be pulled up to VSYS.

Note: Driving the EN/PB/VSENSE pin with an external signal is needed to wake-up the PMIC after an I2C OFF request is sent by I2C (I2C_OFF_REQ). If an OFF request is sent by I2C and the EN/PB/VSENSE is not driven by an external signal, a power cycle on VSYS must be performed to transfer the PMIC from Initialize state to Active.

Table 9-3 Digital Signals Requirements
Digital PinExternal Connection
nINTOpen-drain output. Requires external pull-up.
nRSTOUTOpen-drain output. Requires external pull-up.
EN/PB/VSENSEWhen configured as EN, this signal can be driven by external logic to enable the PMIC.

When configured as PB, this signal requires a pull-up resistor connected to the VSYS pin. Push-button is optional.

When configured as VSENSE, this signal requires an external resistor divider to monitor the pre-regulator.

SDA I2C clock signal. Requires external pull-up.
SCLI2C data signal. Requires external pull-up.
GPIO/VSELWhen configured as GPIO, this pin requires external pull-up.

When configured as VSEL, the initial state (pull-up or pull-down) must be set before the assigned PMIC rail ramps up. For example, if this pin is used to set the voltage on BUCK3, the state must be set before BUCK3 powers up.

GPO/nWAKEUPOpen-drain general purpose output or power-on event signal for the host. Requires external pull-up.
MODE/STBYInput digital pin. The initial state (pull-up or pull-down) must be set before the power-up sequence is complete.