SLVSHK7A March   2025  – December 2025 TPS65214

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  System Control Thresholds
    6. 6.6  BUCK1, BUCK2, BUCK3 Converter
    7. 6.7  General Purpose LDOs (LDO1, LDO2)
    8. 6.8  GPIOs and multi-function pins (EN/PB/VSENSE, nRSTOUT, nINT, GPO/nWAKEUP, GPIO/VSEL, MODE/STBY)
    9. 6.9  Voltage and Temperature Monitors
    10. 6.10 I2C Interface
    11. 6.11 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power-Up Sequencing
      2. 7.3.2  Power-Down Sequencing
      3. 7.3.3  Push Button and Enable Input (EN/PB/VSENSE)
      4. 7.3.4  OFF-Request by I2C Command
      5. 7.3.5  First Supply Detection (FSD)
      6. 7.3.6  Input Voltage Slew Rate With Automatic Power-up
      7. 7.3.7  Buck Converters (Buck1, Buck2, and Buck3)
      8. 7.3.8  Linear Regulators (LDO1 and LDO2)
      9. 7.3.9  Reset to SoC (nRSTOUT)
      10. 7.3.10 Interrupt Pin (nINT)
      11. 7.3.11 PWM/PFM and Low Power Modes (MODE/STBY)
      12. 7.3.12 General Purpose Input/Output and Voltage Select Pin (GPIO/VSEL)
      13. 7.3.13 General Purpose Output and nWAKEUP (GPO/nWAKEUP)
      14. 7.3.14 RESET-Request by I2C Command
      15. 7.3.15 Register Access Control
      16. 7.3.16 I2C-Compatible Interface
        1. 7.3.16.1 Data Validity
        2. 7.3.16.2 Start and Stop Conditions
        3. 7.3.16.3 Transferring Data
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
        1. 7.4.1.1 OFF State
        2. 7.4.1.2 INITIALIZE State
        3. 7.4.1.3 ACTIVE State
        4. 7.4.1.4 STBY State
        5. 7.4.1.5 SLEEP State
        6.       49
        7. 7.4.1.6 Fault Handling
  9. 8 User Registers
    1. 8.1 Device Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Typical Application Example
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
        1. 9.2.3.1 Application Curves
        2. 9.2.3.2 Buck1, Buck2, Buck3 Design Procedure
        3. 9.2.3.3 LDO1, LDO2 Design Procedure
        4. 9.2.3.4 VSYS, VDD1P8
        5. 9.2.3.5 Digital Signals Design Procedure
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

9.4.1 Layout Guidelines

For all switching power supplies, the layout is an important step in the design. If the layout is not carefully done, the regulators can have stability and EMI issues. Therefore, use wide and short traces for the main current path and for the power ground tracks. The input capacitors, output capacitors, and inductors must be placed as close as possible to the device. The output capacitors must have a low impedance to ground. Use multiple VIAS (at least three) directly at the ground landing pad of the capacitor. Here are some layout guidelines:

  • PVIN_Bx: Place the input capacitor as close to the IC as allowed by the layout DRC rules. Any extra parasitic inductance between the input cap and the PVIN_Bx pin can create a voltage spike. Use wide, short traces or polygon to help minimize trace inductance. Do not route any sensitive signals close to the input cap and the device pin as this node has high frequency switching currents. Add 3-4 vias per amp of current on the GND pads for each DCDC. If there is limited space that does not allow for the placement of the input capacitors on the same layer as the PMIC, then place the input capacitors on the opposite layer with VIAS.
  • LX_Bx: Place the inductor close to the PMIC without compromising the PVIN input caps and use short and wide traces or polygons to connect the pin to the inductor. Do not route any sensitive signals close to this node. The inductor must be placed in the same layer as the IC to prevent having to use VIAS in the SW node. The SW-node is the main generator of EMI due to voltage swings from the input voltage to ground with very fast rise and fall times. If needed, to reduce EMI, a RC snubber can be added to the SW node.
  • FB_Bx: Route each of the FB_Bx pins as a trace to the output capacitor. Do not extend the output voltage polygon to the FB_Bx pin as this pin requires to be routed as a trace. The trace resistance from the output capacitor to the FB_Bx pin must be less than 1Ω. The TPS65214 does not support remote sensing so the FB_Bx pins must be connected to the local capacitor of the PMIC. Avoid routing the FB_Bx close to any noisy signals such as the switch node or under the inductor to avoid coupling. If space is constraint, FB_Bx pin can be routed through an inner layer. See example layout.
  • Bucks Cout: The local output capacitors must be placed as close to the inductor as possible to minimize electromagnetic emissions.
  • VSYS/PVIN_LDO12: Place the input capacitor as close as possible to the VSYS/PVIN_LDO12 pin. Route this input trace away from PVIN_Bx to minimize noise coupling. If the space is limited and does not allow placement of the input capacitors on the same layer as the PMIC, then place the input capacitors on the opposite layer with VIAS, close to the IC.
  • VLDOx: Place the output capacitor close to the VLDOx pin. For the LDO regulators, the feedback connection is internal. Therefore, keep the PCB resistance between LDO output and target load in the range of the acceptable voltage, IR, drop for LDOs.
  • VDD1P8: Place the 2.2uF cap as close as possible to the VDD1P8 pin. This capacitor needs to be placed in the same layer as the IC. Two to Three VIAS can be used to connect the GND side of the capacitor to the GND plane of the PCB.
  • Power Pad: The thermal pad must be connected to the PCB ground plane with a minimum of two VIAS.
  • AGND: Do not connect AGND to the power pad (or thermal pad). The AGND pin must be connected to the PCB ground planes through a VIA. Keep the trace from the AGND pin to the VIA short.