The TPS65214 provides three buck converters. Buck1 is capable of supporting up to 2A of load current. Buck2 and Buck3 are capable of supporting up to 2A of load current. The buck converters have an input voltage range from 2.5V - 5.5V, and can be connected either directly to the system power or the output of another buck converter. The output voltage is programmable in the range of 0.6V - 3.4V: in 25mV-steps up to 1.4V, in 100mV-steps between 1.4V and 3.4V.

• The ON/OFF state of the buck converters in ACTIVE state is controlled by the corresponding BUCKx_EN bit in the ENABLE_CTRL register.
• The ON/OFF state of the buck converters in STBY state is controlled by the corresponding BUCKx_STBY_EN bit in the STBY_1_CONFIG register.
• In INITIALIZE and SLEEP state, the buck converters are off, regardless of bit-settings.

• The converters activity can be controlled by the sequencer or through I2C communication.

Buck Switch Modes: Quasi-Fixed-Frequency Mode

The converters can operate in forced-PWM mode, irrespective of load-current, or can be allowed to enter pulse-frequency-modulation (PFM) for low load-currents. The mode is controlled by the MODE/STBY pin when configured as 'MODE' or 'MODE&STBY'. An I2C-command to MODE_I2C_CTRL bit in MFP_1_CONFIG register can also configure the buck converters for forced-PWM or PFM operation. For more details see Pin Configuration and Functions and PWM/PFM and Low Power Modes (MODE/STBY).

• During a transition to ACTIVE state or to INITIALIZE state, the buck converters operate in forced-PWM, irrespective of the pin-state. PFM-entry is allowed once the device enters the ACTIVE state, upon completion of the sequence and expiration of the last power-up slot.
• In case of a DVFS-induced output voltage change, the TPS65214 temporarily forces the buck-regulators into PWM until the voltage change is completed. If PFM is allowed, the entry and exit into PFM is load-current dependent. PFM starts when the inductor current reaches 0A, which is the case at a load current approximately calculated by:

Configurable Converter Bandwidth

The converters can be individually configured further for a high-bandwidth-mode for optimum transient-response or lower bandwidth, allowing minimum output filter capacitance. The selection is done by the BUCKx_BW_SEL bits in GENERAL_CONFIG register. This bit must only change if this regulator is not enabled. Please note the higher output-capacitance requirements for high bandwidth use case.

Externally Configurable Output Voltage

If GPIO/VSEL is configured as 'VSEL' by bit GPIO_VSEL_CONFIG in register MFP_1_CONFIG, the output voltage of Buck1 or Buck3 can be controlled by pulling the GPIO/VSEL pin high, low or leave the pin floating. These settings support multiple core supply voltages or DDR3LV, DDR4, and DDR4LV supply voltages without an NVM change. See General Purpose Inputs/Outputs and Voltage Select Pin (GPIO/VSEL) for details.

Active Discharge

The buck converters have an active discharge function. The discharge function can be deactivated individually per rail in the DISCHARGE_CONFIG register. If discharge is enabled, the device discharges the output is discharged to ground whenever a rail is deactivated.

• Prior to enabling a rail in the power sequence, the device discharges the rail to avoid starting into a pre-biased output.
• If a rail is enabled by an I2C-command, active discharge is not enforced, but the rail is only enabled if the output voltage is below the SCG-threshold.
• This register is not NVM-backed and does reset if the device enters OFF-state.
• When in INITIALIZE state (during RESET or an I2C-OFF-request), the discharge configuration is not reset. Note: the power-down-sequence can be violated if the discharge function is not enabled.

Dynamic Voltage Scaling

All buck converters support Dynamic Voltage Frequency Scaling (DVFS). The output-voltage can be changed during the operation to optimize the operating voltage for the operation point of the SoC in the lower output voltage range between 0.6V and 1.375V. The voltage change is controlled by writing to BUCKx_VSET in the corresponding BUCKx_VOUT register. During a DVFS-induced voltage transition, the active discharge function is temporarily enabled, irrespective of the discharge-configuration.

The buck converters can be configured for DVFS upon STBY-request via the MODE/STBY pin or I2C. When a STBY-request is received, all bucks that are enabled in the STBY_1_CONFIG register and configured for DVFS by bit BUCKx_DVS_STBY are changed to the output voltages specified by BUCKx_VSET_STBY in the corresponding BUCKx_VOUT_STBY registers. If BUCKx_DVS_STBY is cleared while in STBY, the output voltage reverts to BUCKx_VSET. If BUCKx_DVS_STBY is not set, the corresponding BUCKx output voltage is not changed when transitioning from the ACTIVE to STBY state. When transitioning back to ACTIVE state, the output voltage reverts to BUCKx_VSET.

Figure 7-6 Buck DVS Timing Diagram

Output Capacitance Requirements

• For low-bandwidth configuration, a minimum capacitance of 10uF is required and a maximum total capacitance of 75uF is supported
• For high-bandwidth configuration, a minimum capacitance of 30uF is required and a maximum total capacitance of 220uF is supported

Buck Fault Handling

Undervoltage (UV) monitoring

The TPS65214 detects undervoltages on the buck converter outputs. The undervoltage threshold is configured by the BUCKx_UV_THR bit in the BUCKx_VOUT register. The reaction to an undervoltage detection is dependent on the configuration of the respective BUCKx_UV_MASK bit and the MASK_EFFECT bit in the MASK_CONFIG register. If not masked, the device sets the respective INT_BUCK_1_2_IS_SET or INT_BUCK_3_IS_SET bit in the INT_SOURCE register. The device also sets the corresponding BUCKx_UV bit in the INT_BUCK_1_2 or INT_BUCK_3 register.

During a voltage transition (for example, when triggered by a DVFS induced voltage change), the device blanks the undervoltage detection by default and activates the undervoltage detection when the voltage transition completed. If the device detects an undervoltage during the sequence into ACTIVE state (from INITIALIZE or STBY) and UV is not masked, the power-down-sequence starts at the end of the current slot.

If the device detects an undervoltage in ACTIVE-state or STBY-state and UV is not masked by bit BUCKx_UV_MASK in register INT_MASK_UV, the power-down sequence starts immediately. OC-detection is not maskable.

The TPS65214 provides cycle-by-cycle current-limit on the buck converter outputs. If the device detects over-current for t_{DEGLITCH_OC_short}, respectively for t_{DEGLITCH_OC_long} (configurable individually per rail with EN_LONG_DEGL_FOR_OC_BUCKx in OC_DEGL_CONFIG register; applicable for rising-edge only), the device sets INT_BUCK_1_2_IS_SET respectively INT_BUCK_3_IS_SET bit in INT_SOURCE register and bit BUCKx_OC (for positive over-current) respectively BUCKx_NEG_OC (for negative over-current) in INT_BUCK_1_2 respectively INT_BUCK_3 register.

During a voltage transition (for example, when triggered by a DVFS induced voltage change), the over current detection is blanked and only gets activated when the voltage transition is completed.

If the over-current occurs during the sequence into ACTIVE state (from INITIALIZE or STBY), the device deactivates the affected rail immediately and starts the power-down-sequence at the end of the current slot.

If the over-current occurs in ACTIVE-state or STBY-state, the device deactivates the affected rail immediately and starts the power-down sequence.

OC-detection is not maskable, but the deglitch-time is configurable. TI recommends configuring the shortest deglitch time, t_{DEGLITCH_OC_short}. Extended over-current can lead to increased aging or overshoot upon recovery.

The TPS65214 detects short-to-ground (SCG) faults on the buck-outputs. The reaction to the detection of an SCG event is to set INT_BUCK_1_2_IS_SET respectively INT_BUCK_3_IS_SET bit in INT_SOURCE register and bit BUCKx_SCG in INT_BUCK_1_2 respectively INT_BUCK_3 register. The affected rail is deactivated immediately. The device sequences down all outputs and transitions into the INITIALIZE state.

SCG-detection is not maskable.

If a rail gets enabled, the device blanks SCG detection initially to allow the rail to ramp above the SCG-threshold.

The TPS65214 detects residual voltage (RV) faults on the buck-outputs. The reaction to the detection of an RV event is to set INT_RV_IS_SET bit in INT_SOURCE register and bit BUCKx_RV in INT_RV register. The RV-detection is not maskable, but the nINT-reaction can be configured globally for all rails by MASK_INT_FOR_RV in INT_MASK_WARM register. The BUCKx_RV-flag is set regardless of masking, INT_RV_IS_SET bit is only set if nINT is asserted. The fault-reaction time and potential state-transition depends on the situation when residual voltage is detected:

• If the device detects residual voltage during power-up, ACTIVE_TO_STANDBY, or STANDBY_TO_ACTIVE sequences, the sequence is aborted and the device powers down. The shutdown-fault-reaction is maskable by bit BYPASS_RV_FOR_RAIL_ENABLE in register GENERAL_CONFIG.
• If the device detects residual voltage for more than 80ms on any rail that was deactivated during STBY state during a request to leave STBY state, the device transitions into INITIALIZE state. The device sets the BUCKx_RV-bit if the condition persists for 4ms to 5ms, but less than 80ms.
• If residual voltage is detected during an EN-command of the rail by I2C, the BUCKx_RV-flag is set immediately, but no state transition occurs.

The buck converters have a local over-temperature sensor. The reaction to a temperature warning is dependent on the configuration of the respective SENSOR_x_WARM_MASK bit in MASK_CONFIG register and the MASK_EFFECT bits in INT_MASK_BUCKS register. If the temperature at the sensor exceeds T_{WARM_Rising} and is not masked, the device sets INT_SYSTEM_IS_SET bit in INT_SOURCE register and SENSOR_x_WARM bit in INT_SYSTEM register. In case the sensor detects a temperature exceeding T_{HOT_Rising} , the converters power dissipation and junction temperature exceeds safe operating value. The device powers down all active outputs immediately and sets INT_SYSTEM_IS_SET bit in INT_SOURCE register and SENSOR_x_HOT bit in INT_SYSTEM register. The TPS65214 automatically recovers once the temperature drops below the T_{WARM_Falling} threshold value (or below the T_{HOT_Falling} threshold value in case T_WARM is masked). The _HOT bit remains set and needs to be cleared by writing '1'. The HOT-detection is not maskable.