SLVSHK7A March   2025  – December 2025 TPS65214

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  System Control Thresholds
    6. 6.6  BUCK1, BUCK2, BUCK3 Converter
    7. 6.7  General Purpose LDOs (LDO1, LDO2)
    8. 6.8  GPIOs and multi-function pins (EN/PB/VSENSE, nRSTOUT, nINT, GPO/nWAKEUP, GPIO/VSEL, MODE/STBY)
    9. 6.9  Voltage and Temperature Monitors
    10. 6.10 I2C Interface
    11. 6.11 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power-Up Sequencing
      2. 7.3.2  Power-Down Sequencing
      3. 7.3.3  Push Button and Enable Input (EN/PB/VSENSE)
      4. 7.3.4  OFF-Request by I2C Command
      5. 7.3.5  First Supply Detection (FSD)
      6. 7.3.6  Input Voltage Slew Rate With Automatic Power-up
      7. 7.3.7  Buck Converters (Buck1, Buck2, and Buck3)
      8. 7.3.8  Linear Regulators (LDO1 and LDO2)
      9. 7.3.9  Reset to SoC (nRSTOUT)
      10. 7.3.10 Interrupt Pin (nINT)
      11. 7.3.11 PWM/PFM and Low Power Modes (MODE/STBY)
      12. 7.3.12 General Purpose Input/Output and Voltage Select Pin (GPIO/VSEL)
      13. 7.3.13 General Purpose Output and nWAKEUP (GPO/nWAKEUP)
      14. 7.3.14 RESET-Request by I2C Command
      15. 7.3.15 Register Access Control
      16. 7.3.16 I2C-Compatible Interface
        1. 7.3.16.1 Data Validity
        2. 7.3.16.2 Start and Stop Conditions
        3. 7.3.16.3 Transferring Data
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
        1. 7.4.1.1 OFF State
        2. 7.4.1.2 INITIALIZE State
        3. 7.4.1.3 ACTIVE State
        4. 7.4.1.4 STBY State
        5. 7.4.1.5 SLEEP State
        6.       49
        7. 7.4.1.6 Fault Handling
  9. 8 User Registers
    1. 8.1 Device Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Typical Application Example
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
        1. 9.2.3.1 Application Curves
        2. 9.2.3.2 Buck1, Buck2, Buck3 Design Procedure
        3. 9.2.3.3 LDO1, LDO2 Design Procedure
        4. 9.2.3.4 VSYS, VDD1P8
        5. 9.2.3.5 Digital Signals Design Procedure
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

7.3.10 Interrupt Pin (nINT)

During power-up, the output of the nINT pin does depend on whether any INT_SOURCE flags are set and the configuration of the MASK_EFFECT bit in INT_MASK_BUCKS register-. If one or more flags are set, then nINT pin is pulled low and is only released high after those flags have been cleared by writing ‘1’ to them. Note, the nINT-pin can only transition 'high' if a VIO-voltage for the pull-up is available.

In SLEEP state, the nINT pin is always released high. In ACTIVE or STBY state, the nINT pin can be driven low to signal an event or fault condition to the host processor. Whenever a fault or event occurs in the IC, the corresponding interrupt bit is set in the INT register, and the open-drain output is driven low. In case the device transitions to INITIALIZE state, the nINT pin is pulled low as well, regardless if the transition is triggered by an OFF-request or a fault.

If the fault is no longer present, a W1C (write '1' to clear) needs to be performed on the failure bits. This command also allows the nINT-pin to release (return to Hi-Z state). If the failure persists, the corresponding bit remains set and the INT pin remains low.

The UV-faults can be individually masked per rail in INT_MASK_UV registers. The thermal sensors can individually be masked by SENSOR_x_WARM_MASK in the MASK_CONFIG register. The effect of the masking for UV and WARM is defined globally by MASK_EFFECT bits in MASK_CONFIG register.

The nINT reaction for RV-faults is defined globally by MASK_INT_FOR_RV bits in MASK_CONFIG register.

  • 00b = no state change, no nINT reaction, no bit set
  • 01b = no state change, no nINT reaction, bit set
  • 10b = no state change, nINT reaction, bit set (same as 11b)
  • 11b = no state change, nINT reaction, bit set (same as 10b)
CAUTION: Masking poses a risk to the device or the system. In case the masking is performed by I2C-command, the masking bits do get reset to NVM-based default after transitioning to INITIALIZE state. Bits corresponding to faults newly configured via I2C as SD-faults do not get cleared.

TI does not recommend masking OC- and UV-detection on the same rail.