SLVSHK7A March   2025  – December 2025 TPS65214

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  System Control Thresholds
    6. 6.6  BUCK1, BUCK2, BUCK3 Converter
    7. 6.7  General Purpose LDOs (LDO1, LDO2)
    8. 6.8  GPIOs and multi-function pins (EN/PB/VSENSE, nRSTOUT, nINT, GPO/nWAKEUP, GPIO/VSEL, MODE/STBY)
    9. 6.9  Voltage and Temperature Monitors
    10. 6.10 I2C Interface
    11. 6.11 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power-Up Sequencing
      2. 7.3.2  Power-Down Sequencing
      3. 7.3.3  Push Button and Enable Input (EN/PB/VSENSE)
      4. 7.3.4  OFF-Request by I2C Command
      5. 7.3.5  First Supply Detection (FSD)
      6. 7.3.6  Input Voltage Slew Rate With Automatic Power-up
      7. 7.3.7  Buck Converters (Buck1, Buck2, and Buck3)
      8. 7.3.8  Linear Regulators (LDO1 and LDO2)
      9. 7.3.9  Reset to SoC (nRSTOUT)
      10. 7.3.10 Interrupt Pin (nINT)
      11. 7.3.11 PWM/PFM and Low Power Modes (MODE/STBY)
      12. 7.3.12 General Purpose Input/Output and Voltage Select Pin (GPIO/VSEL)
      13. 7.3.13 General Purpose Output and nWAKEUP (GPO/nWAKEUP)
      14. 7.3.14 RESET-Request by I2C Command
      15. 7.3.15 Register Access Control
      16. 7.3.16 I2C-Compatible Interface
        1. 7.3.16.1 Data Validity
        2. 7.3.16.2 Start and Stop Conditions
        3. 7.3.16.3 Transferring Data
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
        1. 7.4.1.1 OFF State
        2. 7.4.1.2 INITIALIZE State
        3. 7.4.1.3 ACTIVE State
        4. 7.4.1.4 STBY State
        5. 7.4.1.5 SLEEP State
        6.       49
        7. 7.4.1.6 Fault Handling
  9. 8 User Registers
    1. 8.1 Device Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Typical Application Example
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
        1. 9.2.3.1 Application Curves
        2. 9.2.3.2 Buck1, Buck2, Buck3 Design Procedure
        3. 9.2.3.3 LDO1, LDO2 Design Procedure
        4. 9.2.3.4 VSYS, VDD1P8
        5. 9.2.3.5 Digital Signals Design Procedure
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

7.3.3 Push Button and Enable Input (EN/PB/VSENSE)

The EN/PB/VSENSE pin is used to enable the PMIC. The pin can be configured in three ways:

Device Enable (EN)

When configured as EN, this pin needs to be pulled high to generate an ON-request. Pulling this pin low generates an OFF-request.

  • The deglitch-time of the EN-pin is configured by EN_PB_VSENSE_DEGL in MFP_2_CONFIG register.
  • The power-up sequence starts if the EN input is above the VIL-threshold low for the configured tDEGL_EN_Rise.
  • To signify the power-up based on an EN/PB/VSENSE pin-event, the device sets bit POWER_UP_FROM_EN_PB_VSENSE in POWER_UP_STATUS_REG register. This bit does not assert the nINT pin. Write W1C to clear the bit.
  • The power-down sequence starts if the EN input is below the VIH-threshold for tDEGL_EN_Fall.
  • In case of a shut-down fault, no renewed on-request is required. The device automatically executes the power-up sequence if EN input is still above the VIH-threshold. (EN considered level-sensitive)
  • In case of a cold reset (regardless if by RESET-pin or I2C-request), no renewed on-request is required. The device automatically executes the power-up sequence if EN input is still above the VIH-threshold. (EN considered level-sensitive)
  • In case EN is pulled low after entering SLEEP state, the pin must be pulled high again to enter the INITIALIZE state. EN must remain high for tEN_PB_WAKEUP to continue to the ACTIVE state. If EN is pulled low before tEN_PB_WAKEUP elapses, the device re-enters the SLEEP state.

Push-Button (PB)

When configured as PB, a CMOS-type input used to power-up the PMIC. Typically, the PB pin is connected to a momentary switch to ground and an external pullup resistor.

  • The hold-time of the push-button is configured by EN_PB_VSENSE_DEGL in MFP_2_CONFIG register.
  • The power-up sequence starts if the PB input is below the VIL-threshold low for the configured tPB_ON.
  • To signify the power-up based on an EN/PB/VSENSE pin-event, the device sets bit POWER_UP_FROM_EN_PB_VSENSE in POWER_UP_STATUS_REG register. This bit does not assert the nINT pin. Write W1C to clear the bit.
  • The PB pin has a rising-edge deglitch tDEGL_PB_RISE to filter bouncing of the switch
  • The power-down sequence starts if the PB input is held low for tPB_OFF-time (not configurable).
  • In case of a shut-down fault, no renewed on-request is required. The device automatically executes the power-up sequence without a PB-press.
  • In case of a cold reset (regardless if by RESET-pin or I2C-request), no renewed on-request is required. The device automatically executes the power-up sequence without a PB-press.
  • In case the device is in SLEEP state, a falling edge on PB transitions to the INITIALIZE state. PB must remain low for tEN_PB_WAKEUP to continue to the ACTIVE state. If PB is is released before tEN_PB_WAKEUP elapses, the device re-enters the SLEEP state.
  • A push-button press is only recognized after VSYS is above VSYS_POR-threshold or the PB must be held long enough after VSYS is above VSYS_POR-threshold.
  • Following bits in the signify the PB-press events:
    • PB_FALLING_EDGE_DETECTED: PB was pressed for for a time-interval longer than tDEGL_PB_INT since the previous time this bit was cleared. This bit when set, does assert nINT pin (if config bit MASK_INT_FOR_PB='0'). Write W1C to clear.
    • PB_RISING_EDGE_DETECTED: PB was released for a time-interval longer than tDEGL_PB_INT since the previous time this bit was cleared. This bit when set, does assert nINT pin (if config bit MASK_INT_FOR_PB='0'). Write W1C to clear.
    • PB_REAL_TIME_STATUS: Deglitched (tDEGL_PB_INT) real-time status of PB pin. Valid only when EN/PB/VSENSE pin is configured as PB. This bit does not assert the nINT pin.

Power-Fail Comparator Input (VSENSE)

When configured as VSENSE, this pin can be used to sense the supply-voltage of the pre-regulator. Connect a resistor divider from the pre-regulator output to configure the sense voltage.

  • The deglitch-time of the VSENSE-pin is configurable by EN_PB_VSENSE_DEGL in MFP_2_CONFIG register.
  • Power-up is gated by VSYS being above the VSYSPOR_Rising-threshold and the VSENSE input is above the VVSENSE-threshold (not deglitched)
  • The power-up sequence starts if the VSENSE input rises above VVSENSE.
  • To signify the power-up based on an EN/PB/VSENSE pin-event, the device sets bit POWER_UP_FROM_EN_PB_VSENSE in POWER_UP_STATUS_REG register. This bit does not assert the nINT pin. Write W1C to clear the bit.
  • The power-down sequence starts if the VSENSE input falls below the VVSENSE-threshold for tDEGL_VSENSE_Fall, to avoid an un-sequenced power-off due to the loss of VSYS-supply-voltage.
  • In case of a shut-down fault, no renewed on-request is required. The device automatically executes the power-up sequence if VSENSE input is still above the VVSENSE-threshold.
  • In case of a cold reset (regardless if by RESET-pin or I2C-request), no renewed on-request is required. The device automatically executes the power-up sequence if VSENSE input is still above the VVSENSE-threshold.
  • In case the device is in SLEEP state, VSENSE cannot be used to transition directly to the INITIALIZE state. The device can only enter INITIALIZE following the OFF state.