SLVSHK7A March   2025  – December 2025 TPS65214

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  System Control Thresholds
    6. 6.6  BUCK1, BUCK2, BUCK3 Converter
    7. 6.7  General Purpose LDOs (LDO1, LDO2)
    8. 6.8  GPIOs and multi-function pins (EN/PB/VSENSE, nRSTOUT, nINT, GPO/nWAKEUP, GPIO/VSEL, MODE/STBY)
    9. 6.9  Voltage and Temperature Monitors
    10. 6.10 I2C Interface
    11. 6.11 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power-Up Sequencing
      2. 7.3.2  Power-Down Sequencing
      3. 7.3.3  Push Button and Enable Input (EN/PB/VSENSE)
      4. 7.3.4  OFF-Request by I2C Command
      5. 7.3.5  First Supply Detection (FSD)
      6. 7.3.6  Input Voltage Slew Rate With Automatic Power-up
      7. 7.3.7  Buck Converters (Buck1, Buck2, and Buck3)
      8. 7.3.8  Linear Regulators (LDO1 and LDO2)
      9. 7.3.9  Reset to SoC (nRSTOUT)
      10. 7.3.10 Interrupt Pin (nINT)
      11. 7.3.11 PWM/PFM and Low Power Modes (MODE/STBY)
      12. 7.3.12 General Purpose Input/Output and Voltage Select Pin (GPIO/VSEL)
      13. 7.3.13 General Purpose Output and nWAKEUP (GPO/nWAKEUP)
      14. 7.3.14 RESET-Request by I2C Command
      15. 7.3.15 Register Access Control
      16. 7.3.16 I2C-Compatible Interface
        1. 7.3.16.1 Data Validity
        2. 7.3.16.2 Start and Stop Conditions
        3. 7.3.16.3 Transferring Data
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
        1. 7.4.1.1 OFF State
        2. 7.4.1.2 INITIALIZE State
        3. 7.4.1.3 ACTIVE State
        4. 7.4.1.4 STBY State
        5. 7.4.1.5 SLEEP State
        6.       49
        7. 7.4.1.6 Fault Handling
  9. 8 User Registers
    1. 8.1 Device Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Typical Application Example
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
        1. 9.2.3.1 Application Curves
        2. 9.2.3.2 Buck1, Buck2, Buck3 Design Procedure
        3. 9.2.3.3 LDO1, LDO2 Design Procedure
        4. 9.2.3.4 VSYS, VDD1P8
        5. 9.2.3.5 Digital Signals Design Procedure
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

7.3.6 Input Voltage Slew Rate With Automatic Power-up

Note: For a stable power-up, sufficient input-to-output voltage headroom is required for each output rail when the rail is enabled in the power sequence. The required headroom are specified as VHEADROOM_PWM for the buck regulators and VDROPOUT for the LDOs.

In applications where the PMIC is expected to power up automatically with the system input voltage, (for example, when FSD is enabled or EN externally pulled up to VSYS/PVIN_LDO12), the device starts the power sequence after the input voltage reaches VSYSPOR_Rising and tNVM_LOAD elapses. The required input voltage slew rate to support each regulator is calculated based on the headroom requirement and the assigned slot y in the power sequence. For output rails assigned to SLOT_0, the calculation only needs to include tNVM_LOAD. Cases where SRVIN is zero or negative do not need to be considered since the minimum input voltage required for regulation is already met at the VSYSPOR_Rising threshold. For all other cases, the pre-regulator that generates the system input voltage must meet the highest required slew rate.

Equation 1. SRVSYS≥VOUT+VHEADROOM-VSYSPOR_RisingtNVM_LOAD+tSLOT_0+tSLOT_1 + ... + tSLOT_(y-1) (V/ms)

If the highest required slew rate is not supported, the insufficient headroom for the output rail creates a -UV fault once enabled in the power sequence. The device increments RETRY_COUNT and attempts to power up 2 more times as shown in Figure 7-4. If the input voltage still does not provide sufficient headroom for the output rail, the device enters the INITIALIZE state until VSYS/PVIN_LDO12 is cycled to renew an ON-request.

TPS65214 VSYS Slow Ramp With FSD and MASK_RETRY_COUNT_ON_FIRST_PU = '0' Figure 7-4 VSYS Slow Ramp With FSD and MASK_RETRY_COUNT_ON_FIRST_PU = '0'

For applications that require automatic power-up and cannot meet the slew rate requirements, the RETRY_COUNT can be masked on the first power up by bit MASK_RETRY_COUNT_ON_FIRST_PU in register MFP_2_CONFIG. When this bit is set, the device masks RETRY_COUNT until after the power-up sequence is completed as shown in Figure 7-5. After power-up, the RETRY_COUNT is unmasked to enable a device shutdown in the event of a permanent fault.

TPS65214 VSYS Slow Ramp With FSD and MASK_RETRY_COUNT_ON_FIRST_PU = '1' Figure 7-5 VSYS Slow Ramp With FSD and MASK_RETRY_COUNT_ON_FIRST_PU = '1'