SNAS264D April 2006 – February 2024 LM94
PRODUCTION DATA
| Register Address | Read/ Write | Register Name | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 | Default Value |
|---|---|---|---|---|---|---|---|---|---|---|---|
| 37h | R/W | Zone 1 Tcontrol | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 00h |
| 38h | R/W | Zone 2 Tcontrol | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 00h |
Same format as temperature value register for Zone 1 and Zone 2. The PWM output controls the airflow over the processors and thus the temperature of the processors is adjusted by the PI loop to maintain the hottest Zone 1 or Zone 2 temperature reading between their respective values for Tcontrol and Tcontrol - hysteresis. Intel specifies an optimum Tcontrol temperature for some of it's processors that can be found in the MSR register space.