SPRACW9A June   2021  – March 2023 TMS320F2800132 , TMS320F2800132 , TMS320F2800133 , TMS320F2800133 , TMS320F2800135 , TMS320F2800135 , TMS320F2800137 , TMS320F2800137 , TMS320F2800152-Q1 , TMS320F2800152-Q1 , TMS320F2800153-Q1 , TMS320F2800153-Q1 , TMS320F2800154-Q1 , TMS320F2800154-Q1 , TMS320F2800155 , TMS320F2800155 , TMS320F2800155-Q1 , TMS320F2800155-Q1 , TMS320F2800156-Q1 , TMS320F2800156-Q1 , TMS320F2800157 , TMS320F2800157 , TMS320F2800157-Q1 , TMS320F2800157-Q1 , TMS320F280021 , TMS320F280021 , TMS320F280021-Q1 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280023C , TMS320F280025 , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280025C-Q1 , TMS320F280033 , TMS320F280033 , TMS320F280034 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C , TMS320F280039C-Q1 , TMS320F280039C-Q1 , TMS320F280040-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C , TMS320F280049C-Q1 , TMS320F280049C-Q1 , TMS320F28075 , TMS320F28075 , TMS320F28075-Q1 , TMS320F28075-Q1 , TMS320F28076 , TMS320F28076 , TMS320F28374D , TMS320F28374D , TMS320F28374S , TMS320F28374S , TMS320F28375D , TMS320F28375D , TMS320F28375S , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28375S-Q1 , TMS320F28376D , TMS320F28376D , TMS320F28376S , TMS320F28376S , TMS320F28377D , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28377D-Q1 , TMS320F28377S , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28377S-Q1 , TMS320F28378D , TMS320F28378D , TMS320F28378S , TMS320F28378S , TMS320F28379D , TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379D-Q1 , TMS320F28379S , TMS320F28379S , TMS320F28384D , TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388D , TMS320F28388S , TMS320F28388S , TMS320F28P650DH , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P650SK , TMS320F28P659DK-Q1 , TMS320F28P659DK-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Memory Cross-Talk Challenges
    2. 1.2 Resources for Signal Conditioning Circuit Design
      1. 1.2.1 TI Precision Labs - SAR ADC Input Driver Design Series
      2. 1.2.2 Analog Engineer's Calculator
      3. 1.2.3 Related Application Reports
      4. 1.2.4 TINA-TI SPICE-Based Analog Simulation Program
      5. 1.2.5 PSPICE for TI
      6. 1.2.6 ADC Input Circuit Evaluation for C2000 MCUs
      7. 1.2.7 Charge-Sharing Driving Circuits for C2000 ADCs
  4. 2Review of ADC Input Settling
    1. 2.1 Mechanism of ADC Input Settling
    2. 2.2 Symptoms of Inadequate Settling
      1. 2.2.1 Distortion
      2. 2.2.2 Memory Cross-Talk
      3. 2.2.3 Accuracy
    3. 2.3 C2000 ADC Architecture
  5. 3Problem Statement
    1. 3.1 Example System
    2. 3.2 S+H Settling Analysis
    3. 3.3 Charge-Sharing Analysis
    4. 3.4 Problem Summary
  6. 4Dedicated ADC Sampling
    1. 4.1 Dedicated ADC Concept
    2. 4.2 Settling Mechanism for Dedicated ADC
    3. 4.3 Design Flow for Dedicated ADC
    4. 4.4 Simulating Settling Performance for a Dedicated ADC Circuit
  7. 5Pre-Sampling VREFLO
    1. 5.1 VREFLO Sampling Concept
    2. 5.2 Properties of VREFLO Sampling Method Error
    3. 5.3 Gain Error Compensation
      1. 5.3.1 Methods for Determining Compensation Coefficients
    4. 5.4 VREFLO Sampling Design Flow
    5. 5.5 Discussion of VREFLO Sampling Sequences
  8. 6Summary
  9. 7References
  10. 8Revision History

3.2 S+H Settling Analysis

As presented in Charge-Sharing Driving Circuits for C2000 ADCs, an approximation of the required settling time can be determined using an RC settling model. The time constant for the model is given by the equation:

Equation 1. GUID-CD1F9E08-4B5E-4A05-A24D-71E0AE32B960-low.gif

And the number of time constants needed is given by the equation:

Equation 2. GUID-EFE631A3-A0D1-4D44-81DA-D8586C6E0AC6-low.gif

So the total S+H time should be set to approximately:

Equation 3. GUID-B22229B8-FA5C-41A0-8813-6DC10FEFFF74-low.gif

Where the following parameters are provided by the ADC input model in the device-specific data manual:

  • n = ADC resolution (in bits)
  • RON = ADC sampling switch resistance (in Ohms)
  • CH = ADC sampling capacitor (in pF)
  • CP = ADC channel parasitic input capacitance (in pF)

The following parameters are dependent on the application design:

  • Settling error = tolerable settling error (in LSBs)
  • Rs = ADC driving circuit source impedance (in Ω)
  • CS = capacitance on ADC input pin (in pF)

Table 3-1 shows the settling time calculation using the values from the F280049 data manual and 250pF for CS. Rs is set to 7444Ω, which is the effective impedance of the voltage divider formed by the 1MΩ and 7.5 kΩ resistors (1MΩ || 7.5 kΩ).

Table 3-1 Settling Time for V2 Circuit
Parameter Example 1
CS 250 pF
CH 12.5 pF
Cp 10 pF
Rs

7444Ω
RON 500Ω
n 12 bits
settling error

0.5 LSBs
τ 1.96 µs
k

6.015
Settling time 11.8 µs

This analysis indicates that a settling time of 11.8 µs would be needed to achieve full 12-bit settling performance. This is, unfortunately, much longer than the maximum S+H time that the F280049 device's ADCs can be configured for. Furthermore, this is even longer than the 10 µs triggering period resulting from the 100 kHz ePWM trigger source. The latency resulting from such a long S+H window is also likely to be quite detrimental to the control system's performance. Overall, it will not be possible to get good settling performance just by configuring the correct S+H time.

Figure 3-3 shows the results of simulating Figure 3-2 while setting the S+H time to 100 ns. This time is much less than the 11.8 µs estimated to give full 12-bit settling performance, but represents what might be reasonably configured given the 100 kHz sample rate and a desire for low latency sampling. The simulation shows 131 mV of settling error after the 100 ns S+H window, which is about 4% of the ADC's 3.0 V range. This is quite poor performance considering that an ideal 12-bit ADC is capable of resolving steps of about 0.02% of the ADC's full-scale range.

GUID-DB224F1F-C7D0-4813-9999-DB684EC08A6F-low.png Figure 3-3 Settling Simulation for V2 Circuit With 100 ns S+H