SPRACW9A June   2021  – March 2023 TMS320F2800132 , TMS320F2800132 , TMS320F2800133 , TMS320F2800133 , TMS320F2800135 , TMS320F2800135 , TMS320F2800137 , TMS320F2800137 , TMS320F2800152-Q1 , TMS320F2800152-Q1 , TMS320F2800153-Q1 , TMS320F2800153-Q1 , TMS320F2800154-Q1 , TMS320F2800154-Q1 , TMS320F2800155 , TMS320F2800155 , TMS320F2800155-Q1 , TMS320F2800155-Q1 , TMS320F2800156-Q1 , TMS320F2800156-Q1 , TMS320F2800157 , TMS320F2800157 , TMS320F2800157-Q1 , TMS320F2800157-Q1 , TMS320F280021 , TMS320F280021 , TMS320F280021-Q1 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280023C , TMS320F280025 , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280025C-Q1 , TMS320F280033 , TMS320F280033 , TMS320F280034 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C , TMS320F280039C-Q1 , TMS320F280039C-Q1 , TMS320F280040-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C , TMS320F280049C-Q1 , TMS320F280049C-Q1 , TMS320F28075 , TMS320F28075 , TMS320F28075-Q1 , TMS320F28075-Q1 , TMS320F28076 , TMS320F28076 , TMS320F28374D , TMS320F28374D , TMS320F28374S , TMS320F28374S , TMS320F28375D , TMS320F28375D , TMS320F28375S , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28375S-Q1 , TMS320F28376D , TMS320F28376D , TMS320F28376S , TMS320F28376S , TMS320F28377D , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28377D-Q1 , TMS320F28377S , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28377S-Q1 , TMS320F28378D , TMS320F28378D , TMS320F28378S , TMS320F28378S , TMS320F28379D , TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379D-Q1 , TMS320F28379S , TMS320F28379S , TMS320F28384D , TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388D , TMS320F28388S , TMS320F28388S , TMS320F28P650DH , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P650SK , TMS320F28P659DK-Q1 , TMS320F28P659DK-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Memory Cross-Talk Challenges
    2. 1.2 Resources for Signal Conditioning Circuit Design
      1. 1.2.1 TI Precision Labs - SAR ADC Input Driver Design Series
      2. 1.2.2 Analog Engineer's Calculator
      3. 1.2.3 Related Application Reports
      4. 1.2.4 TINA-TI SPICE-Based Analog Simulation Program
      5. 1.2.5 PSPICE for TI
      6. 1.2.6 ADC Input Circuit Evaluation for C2000 MCUs
      7. 1.2.7 Charge-Sharing Driving Circuits for C2000 ADCs
  4. 2Review of ADC Input Settling
    1. 2.1 Mechanism of ADC Input Settling
    2. 2.2 Symptoms of Inadequate Settling
      1. 2.2.1 Distortion
      2. 2.2.2 Memory Cross-Talk
      3. 2.2.3 Accuracy
    3. 2.3 C2000 ADC Architecture
  5. 3Problem Statement
    1. 3.1 Example System
    2. 3.2 S+H Settling Analysis
    3. 3.3 Charge-Sharing Analysis
    4. 3.4 Problem Summary
  6. 4Dedicated ADC Sampling
    1. 4.1 Dedicated ADC Concept
    2. 4.2 Settling Mechanism for Dedicated ADC
    3. 4.3 Design Flow for Dedicated ADC
    4. 4.4 Simulating Settling Performance for a Dedicated ADC Circuit
  7. 5Pre-Sampling VREFLO
    1. 5.1 VREFLO Sampling Concept
    2. 5.2 Properties of VREFLO Sampling Method Error
    3. 5.3 Gain Error Compensation
      1. 5.3.1 Methods for Determining Compensation Coefficients
    4. 5.4 VREFLO Sampling Design Flow
    5. 5.5 Discussion of VREFLO Sampling Sequences
  8. 6Summary
  9. 7References
  10. 8Revision History

2.2 Symptoms of Inadequate Settling

Once a voltage has been captured into the S+H capacitor, the ADC will translate this voltage into a digital conversion result during the conversion phase. The CPU can then use this result to control or monitor the system. However, if the captured voltage does not accurately represent the applied voltage due to settling error, the final conversion result will have errors even if the ADC conversion process is perfect.

These settling errors will manifest differently depending on whether the ADC is sampling the same channel repeatedly or scanning through multiple channels in a sequence. The settling errors will also manifest differently depending on the starting voltage on the S+H capacitor at the beginning of the acquisition phase. Some ADC architectural implementations will have a starting S+H voltage close to the previously sampled voltage while other architectures will usually start the acquisition phase with a discharged S+H capacitor.