Consider a system with the following ADC parameters:

• F280049 C2000 MCU operating in 12-bit external reference mode
• The ADCs are driven by an 100kHz ePWM trigger source (ePWM1 SOCA)
• Two ADCs are used: ADCA and ADCB
• Four voltages to are converted: V1 through V4
• V1 and V2 are assigned to ADCA and V3 and V4 are assigned to ADCB

The timing diagram of the example system can be seen in Figure 3-1.

Figure 3-1 Example System Timings

Furthermore, consider that V2 is a high-voltage sensing circuit that uses a voltage divider comprised of a 1MΩ and 7.5kΩ resistors to scale down a 400 V signal to a 3.0 V range compatible with the ADC. The voltage divider directly drives the ADC input (no op-amp is used to buffer in the input) and the external capacitor has been selected to be 250 pF. The schematic for this circuit can be seen in Figure 3-2.

Figure 3-2 Example System Schematic for V2

As the subsequent sections will demonstrate, it would be difficult to select a S+H duration that is long enough for this circuit to achieve acceptable settling performance and the sample rate of 100 kHz rate is also too high to support a charge sharing input design. This will necessitate the alternate methods for mitigating memory cross-talk considered later in this document.