SPRADN4B October   2024  – September 2025 AM62P , AM62P-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
    1. 1.1 User's Guide Usage Guidelines
      1. 1.1.1 Custom Board Schematics Design Guidelines - References Used in the User's Guide
      2. 1.1.2 Processor Family-Specific User's Guide
      3. 1.1.3 Schematic Design Guidelines
      4. 1.1.4 Schematic Review Checklist
        1. 1.1.4.1 Common Checklist for Use With All Schematic Design Guidelines and Schematics Review Sections
          1. 1.1.4.1.1 Custom Board Schematic Design Implementation Checklist Sub-Sections Description
      5. 1.1.5 FAQ Reference for User's Guide Usage During Schematic Self-review
    2. 1.2 AM62Px [AMH] Processor Family List of Processors
    3. 1.3 Updates to Schematics Design Guidelines and Schematics Review Checklist
  5. 2 Related Collaterals
    1. 2.1 Links to Commonly Referenced Collaterals During Custom Board Schematic Design
    2. 2.2 Hardware Design Considerations for Custom Board Design User's Guide
  6. 3 Processor-Specific Information
    1. 3.1 Selection of Processor OPN (Orderable Part Number)
    2. 3.2 Processor-specific Data Sheet Use Case and Version Referenced for User's Guide Edits
    3. 3.3 Peripheral Instance Naming Convention - Data Sheet and TRM
    4. 3.4 Processor Peripherals and IO Connection When Not Used
    5. 3.5 Ordering and Quality Information for AM62Px Processor Family
    6. 3.6 Checklist for Selection of Required Processor GPN (Generic Part Number) and OPN (Ordering Part Number)
  7. 4 Processor Power Architecture
    1. 4.1 Generating Processor-Specific and Peripherals (Attached Device) Supply Rails
      1. 4.1.1 AM62P, AM62P-Q1 Processor Family Power Architecture
        1. 4.1.1.1 Power Management IC (PMIC) Based Power Architecture
          1. 4.1.1.1.1 PMIC Based Power Architecture Checklist for TPS65224x
          2. 4.1.1.1.2 Additional References
        2. 4.1.1.2 Discrete Power Devices (DC/DC, LDO) Based Power Architecture
          1. 4.1.1.2.1 Discrete DC/DCs
          2. 4.1.1.2.2 Discrete LDOs
          3. 4.1.1.2.3 Discrete Power Devices (DC/DC, LDO) Based Power Architecture Checklist
    2. 4.2 Processor Power Rails Supply Control, Sequencing and Supply Overload Protection
      1. 4.2.1 Load Switch (Processor Supply Rail Power Switching)
        1. 4.2.1.1 Load Switch (Processor Supply Rail Power Switching) Checklist
      2. 4.2.2 eFuse IC (Power Switching and Protection)
  8. 5 General Recommendations
    1. 5.1 Processor Performance Evaluation Module (SK - Starter Kit)
      1. 5.1.1 Evaluation Module (Starter Kit) Checklist
    2. 5.2 Processor-Specific SK Versus Data Sheet
      1. 5.2.1 Notes About Component Selection
        1. 5.2.1.1 Series Resistor
        2. 5.2.1.2 Parallel Pull Resistor
        3. 5.2.1.3 Drive Strength Configuration
        4. 5.2.1.4 Processor-specific Data Sheet Recommendations
        5. 5.2.1.5 Processor IOs Protection - Provision for External ESD Protection Devices
        6. 5.2.1.6 Peripheral Clock Outputs Series Resistor
        7. 5.2.1.7 Peripheral Clock Outputs Pulldown Resistor
        8. 5.2.1.8 Component Selection Checklist
      2. 5.2.2 Additional Information Regarding SK Design (Schematic, Board) and Reuse
        1. 5.2.2.1 Updated SK Schematic With Design, Review and CAD Notes Added
          1. 5.2.2.1.1 AM62P, AM62P-Q1 Processor Family
        2. 5.2.2.2 SK Design Files Reuse for Custom Board Design
          1. 5.2.2.2.1 SK Design Files Reuse for Custom Board Design - Checklist
      3. 5.2.3 SK Schematic Pages Sequencing (Based on Functions, Reuse) and SK Board Layout
    3. 5.3 Processor-Specific SDK
    4. 5.4 General Design Recommendations (to Know) Before Starting the Custom Board Design
      1. 5.4.1  Processor Documentation
      2. 5.4.2  Processor Pin Attributes (Pinout) Verification
      3. 5.4.3  Device Comparison, IOSET and Voltage Conflict
      4. 5.4.4  RSVD Reserved Pins (Signals)
      5. 5.4.5  Note on PADCONFIG Registers
      6. 5.4.6  Processor IO (Signal) Isolation for Fail-Safe Operation
      7. 5.4.7  Pin Connectivity Requirements and Reference to Processor-Specific SK
      8. 5.4.8  Custom Board High-Speed Interface Design Guidelines
      9. 5.4.9  Recommendation for LVCMOS (GPIO) Output Current Source or Current Sink
      10. 5.4.10 Connection of Slow Ramp Signal (Input) or Capacitor Load (Output) to Processor IOs
      11. 5.4.11 Processor and Processor Peripherals Design Related Queries During Custom Board Design
      12. 5.4.12 General Design Recommendations (to Know) Before Starting the Custom Board Design Checklist
      13. 5.4.13 Attached Devices Recommendations
  9. 6 Processor-Specific Recommendations for Power, Clock, Reset, Boot and Debug
    1. 6.1 Common (Processor Start-Up) Connections
      1. 6.1.1 Power Supply
        1. 6.1.1.1 Core and Peripherals Supplies
          1. 6.1.1.1.1 Power Supply Ramp (Slew Rate) Requirement and Dynamic Voltage Scaling
          2. 6.1.1.1.2 Additional Information
          3. 6.1.1.1.3 Processor Core and Peripheral Core Power Supply Checklist
          4. 6.1.1.1.4 Peripheral Analog Power Supply Checklist
        2. 6.1.1.2 IO Supply for IO Groups
          1. 6.1.1.2.1 Additional Information
          2. 6.1.1.2.2 IO Supply for IO Groups Checklist
        3. 6.1.1.3 Supply for VPP (eFuse ROM Programming)
          1. 6.1.1.3.1 Supply for VPP Checklist
        4. 6.1.1.4 Supply Connection for Partial IO (Low Power) Mode Configuration
          1. 6.1.1.4.1 Partial IO Mode Functionality
          2. 6.1.1.4.2 Partial IO Low Power Mode When Used
          3. 6.1.1.4.3 Partial IO Low Power Mode When Not Used
          4. 6.1.1.4.4 Processor-specific Data Sheet Reference for Power Sequence
          5. 6.1.1.4.5 Partial IO (Low Power) Mode Checklist
        5. 6.1.1.5 Additional Information
      2. 6.1.2 Capacitors for Supply Rails
        1. 6.1.2.1 AM62P, AM62P-Q1 Processor Family
        2. 6.1.2.2 Additional Information
        3. 6.1.2.3 Capacitors for Supply Rails Checklist
      3. 6.1.3 Processor Clocks (Inputs / Outputs)
        1. 6.1.3.1 Clock Inputs
          1. 6.1.3.1.1 MCU_OSC0 (High Frequency) Clock (Internal Oscillator) or LVCMOS Digital Clock (External Oscillator)
          2. 6.1.3.1.2 WKUP_LFOSC0 (Low Frequency) Clock (Internal Oscillator) or LVCMOS Digital Clock (External Oscillator)
          3. 6.1.3.1.3 EXT_REFCLK1 (External Clock Input to MAIN Domain)
          4. 6.1.3.1.4 Clock Input Checklist - MCU_OSC0
          5. 6.1.3.1.5 Clock Input Checklist - WKUP_LFOSC0
        2. 6.1.3.2 Clock Outputs
          1. 6.1.3.2.1 Clock Output Checklist
      4. 6.1.4 Processor Reset
        1. 6.1.4.1 External Reset Inputs
        2. 6.1.4.2 Reset Status Outputs
        3. 6.1.4.3 Additional Information
        4. 6.1.4.4 Processor Reset Inputs Checklist
        5. 6.1.4.5 Processor Reset Status Outputs Checklist
      5. 6.1.5 Configuration of Boot Modes (for Processor)
        1. 6.1.5.1 Processor Boot Mode Inputs Isolation Buffers Use Case and Optimization
        2. 6.1.5.2 Boot Mode Configuration
          1. 6.1.5.2.1 Notes for USB Boot Mode
        3. 6.1.5.3 Boot Mode Implementation Approaches
        4. 6.1.5.4 Additional Information
        5. 6.1.5.5 Configuration of Boot Modes (for Processor) Checklist
    2. 6.2 Custom Board Debug Using JTAG and EMU
      1. 6.2.1 JTAG Interface and EMU Signals When Used
      2. 6.2.2 JTAG Interface and EMU Signals When Not Used
      3. 6.2.3 Additional Information
      4. 6.2.4 Custom Board Debug Using JTAG and EMU Checklist
  10. 7 Processor Peripherals Power, Interface and Connections
    1. 7.1 Supported Processor Cores and MCU Cores
    2. 7.2 Supply Connections for IO Supply for IO Groups
      1. 7.2.1 AM62P, AM62P-Q1 IO supply
      2. 7.2.2 Supply Connections for IO Supply for IO Groups Checklist
    3. 7.3 Memory Interface (DDRSS (DDR4/LPDDR4), MMCSD (eMMC/SD Card/SDIO), OSPI/QSPI and GPMC)
      1. 7.3.1 DDR Subsystem (DDRSS)
        1. 7.3.1.1 DDR4 SDRAM (Double Data Rate 4 Synchronous Dynamic Random-Access Memory)
          1. 7.3.1.1.1 AM62P, AM62P-Q1 Processor Family
        2. 7.3.1.2 LPDDR4 SDRAM (Low-Power Double Data Rate 4 Synchronous Dynamic Random-Access Memory)
          1. 7.3.1.2.1 AM62P, AM62P-Q1 Processor Family
            1. 7.3.1.2.1.1 Memory Interface Configuration
            2. 7.3.1.2.1.2 Routing Topology and Connection of Memory Terminations
            3. 7.3.1.2.1.3 Resistors for DDRSS Control and Calibration
            4. 7.3.1.2.1.4 Capacitors for the Power Supply Rails
            5. 7.3.1.2.1.5 Data Bit or Byte Swapping
            6. 7.3.1.2.1.6 LPDDR4 Implementation Checklist
      2. 7.3.2 Multi-Media Card/Secure Digital (MMCSD)
        1. 7.3.2.1 MMC0 - eMMC (Embedded Multi-Media Card) Interface
          1. 7.3.2.1.1 AM62P, AM62P-Q1 Processor Family
            1. 7.3.2.1.1.1 MMC0 Interface Used
              1. 7.3.2.1.1.1.1 IO Power Supply
              2. 7.3.2.1.1.1.2 eMMC Interface Signals Connection
              3. 7.3.2.1.1.1.3 eMMC (Attached Device) Reset
              4. 7.3.2.1.1.1.4 Capacitors for the Power Supply Rails
            2. 7.3.2.1.1.2 MMC0 Interface Not Used
            3. 7.3.2.1.1.3 MMC0 (eMMC) Checklist
          2. 7.3.2.1.2 Additional Information on eMMC PHY
          3. 7.3.2.1.3 MMC0 – SD (Secure Digital) Card Interface
        2. 7.3.2.2 MMC1/MMC2 – SD (Secure Digital) Card Interface
          1. 7.3.2.2.1 IO Power Supply
          2. 7.3.2.2.2 Signals Connection
            1. 7.3.2.2.2.1 MMC1 Signals Used for SD Card Interface (Recommended)
            2. 7.3.2.2.2.2 MMC2 Signals Used for SD Card Interface
            3. 7.3.2.2.2.3 Additional Information
          3. 7.3.2.2.3 SD Card Power Supply Switch EN Reset Logic
          4. 7.3.2.2.4 External ESD Protection for the SD Card Interface Signals
          5. 7.3.2.2.5 Capacitors for the IO Supply for IO Groups Supply Rails
          6. 7.3.2.2.6 SD Card Interface (MMC1) Checklist
        3. 7.3.2.3 MMC1/MMC2 SDIO (Embedded) Interface
          1. 7.3.2.3.1 IO Power Supply
          2. 7.3.2.3.2 Signals Connection
          3. 7.3.2.3.3 SDIO (MMC2 Recommended, Embedded) Interface Checklist
        4. 7.3.2.4 Additional Information
      3. 7.3.3 Octal Serial Peripheral Interface (OSPI) or Quad Serial Peripheral Interface (QSPI)
        1. 7.3.3.1 IO Power Supply
        2. 7.3.3.2 Signals Connection
        3. 7.3.3.3 OSPI/QSPI Device Reset
        4. 7.3.3.4 Loopback Clock
        5. 7.3.3.5 Interface to Multiple (Attached) Devices
        6. 7.3.3.6 Capacitors for the Power Supply Rails
        7. 7.3.3.7 OSPI0 or QSPI0 Peripheral Interface Implementation Checklist
      4. 7.3.4 General-Purpose Memory Controller (GPMC)
        1. 7.3.4.1 IO Power Supply
        2. 7.3.4.2 GPMC Interface
        3. 7.3.4.3 Signals Connection
          1. 7.3.4.3.1 GPMC NAND
        4. 7.3.4.4 Memory (Attached Device) Reset
        5. 7.3.4.5 Capacitors for the Power Supply Rails
        6. 7.3.4.6 GPMC Interface Checklist
    4. 7.4 External Communication Interface (Ethernet (CPSW3G0), USB2.0, UART and MCAN)
      1. 7.4.1 Ethernet (MAC) Interface
        1. 7.4.1.1 Common Platform Ethernet Switch 3-port Gigabit (CPSW3G0)
          1. 7.4.1.1.1  IO Power Supply
          2. 7.4.1.1.2  MAC (Data, Control and Clock) Interface Signals Connection
          3. 7.4.1.1.3  EPHy Reset
          4. 7.4.1.1.4  Ethernet PHY (and MAC) Operation and Media Independent Interface (MII) Clock
            1. 7.4.1.1.4.1 Crystal Used as Clock Source for Processor and EPHy
            2. 7.4.1.1.4.2 External Oscillator Used as Clock Source
            3. 7.4.1.1.4.3 Processor Clock Output (CLKOUT0)
          5. 7.4.1.1.5  Ethernet PHY Pin Strapping
          6. 7.4.1.1.6  External Interrupt (EXTINTn)
            1. 7.4.1.1.6.1 External Interrupt (EXTINTn) Checklist
          7. 7.4.1.1.7  MAC (Media Access Controller) to MAC Interface
          8. 7.4.1.1.8  MDIO (Management Data Input/Output) Interface
          9. 7.4.1.1.9  Ethernet MDI (Medium Dependent Interface) Including Magnetics
          10. 7.4.1.1.10 Capacitors for the Power Supply Rails
          11. 7.4.1.1.11 Ethernet Interface Checklist
      2. 7.4.2 Universal Serial Bus (USB2.0)
        1. 7.4.2.1 USBn (n = 0-1) Interface When Used
          1. 7.4.2.1.1 USB Interface Configured as Host
          2. 7.4.2.1.2 USB Interface Configured as Device
          3. 7.4.2.1.3 USB Interface Configured as Dual-Role-Device
          4. 7.4.2.1.4 USB Type-C
        2. 7.4.2.2 USBn (n = 0-1) Interface When Not Used
        3. 7.4.2.3 Additional Information
        4. 7.4.2.4 USB Interface Checklist
      3. 7.4.3 Universal Asynchronous Receiver/Transmitter (UART)
        1. 7.4.3.1 UART Interface When Not Used
        2. 7.4.3.2 Universal Asynchronous Receiver/Transmitter (UART) Checklist
      4. 7.4.4 Modular Controller Area Network (MCAN) with Full CAN-FD Support
        1. 7.4.4.1 Modular Controller Area Network Checklist
    5. 7.5 On-board Synchronous Communication Interface (MCSPI, MCASP and I2C)
      1. 7.5.1 Multichannel Serial Peripheral Interface (MCSPI) and Audio Peripheral - Multichannel Audio Serial Port (MCASP)
        1. 7.5.1.1 Connection of MCSPI and MCASP Interface Signals
        2. 7.5.1.2 MCSPI Interface Checklist
        3. 7.5.1.3 MCASP Interface Checklist
      2. 7.5.2 Inter-Integrated Circuit (I2C)
        1. 7.5.2.1 I2C Interface Signals Connection
        2. 7.5.2.2 I2C (Open-drain Output Type IO Buffer) Interface Checklist
        3. 7.5.2.3 I2C (Emulated Open-drain Output Type IO) Interface Checklist
    6. 7.6 User Interface (CSIRX0, DPI, OLDI0, DSI), GPIO and Hardware Diagnostics
      1. 7.6.1 Camera Serial Interface (CSI-RX, CSI-2, CSIRX0)
        1. 7.6.1.1 CSIRX0 Peripheral When Used
        2. 7.6.1.2 CSIRX0 Peripheral When Not Used
        3. 7.6.1.3 CSIRX0 Peripheral Checklist
      2. 7.6.2 Display Subsystem (DSS)
        1. 7.6.2.1 Display Parallel Interface (DPI)
          1. 7.6.2.1.1 AM62P, AM62P-Q1 Processor Family
            1. 7.6.2.1.1.1 IO Power Supply
            2. 7.6.2.1.1.2 Connection
            3. 7.6.2.1.1.3 DPI (Attached Device) Reset
            4. 7.6.2.1.1.4 DPI Signals Connection
            5. 7.6.2.1.1.5 Capacitors for the Power Supply Rail
            6. 7.6.2.1.1.6 DPI (VOUT0) Peripheral Checklist
        2. 7.6.2.2 Open LVDS Display Interface (OLDI0)
          1. 7.6.2.2.1 AM62P, AM62P-Q1 Processor Family
            1. 7.6.2.2.1.1 OLDI0 Display Interface Used
              1. 7.6.2.2.1.1.1 OLDI0 Interface Compatibility
              2. 7.6.2.2.1.1.2 IO Power Supply
              3. 7.6.2.2.1.1.3 OLDI0 (Attached Device) Reset
              4. 7.6.2.2.1.1.4 Capacitors for the Power Supply Rail
            2. 7.6.2.2.1.2 OLDI0 Peripheral Not Used
            3. 7.6.2.2.1.3 Additional Information
            4. 7.6.2.2.1.4 OLDI0 Peripheral Checklist
        3. 7.6.2.3 Display Serial Interface (DSI)
          1. 7.6.2.3.1 AM62P, AM62P-Q1 Processor Family
            1. 7.6.2.3.1.1 DSITX0 Peripheral Used
              1. 7.6.2.3.1.1.1 DSITX0 Peripheral Checklist
            2. 7.6.2.3.1.2 DSITX0 Peripheral Not Used
      3. 7.6.3 General Purpose Input/Output (GPIO)
        1. 7.6.3.1 Availability of CLKOUT on Processor GPIO
        2. 7.6.3.2 GPIO Connection and Addition of External Buffer
        3. 7.6.3.3 Additional Information
        4. 7.6.3.4 GPIO Checklist
      4. 7.6.4 On-board Hardware Diagnostics
        1. 7.6.4.1 Monitoring of On-board Supply Voltages Using Processor Voltage Monitors
          1. 7.6.4.1.1 Voltage Monitor Inputs Connection When Used
            1. 7.6.4.1.1.1 Voltage Monitor Checklist
          2. 7.6.4.1.2 Voltage Monitor Inputs Connection When Not Used
        2. 7.6.4.2 Internal Temperature Monitoring
          1. 7.6.4.2.1 Internal Temperature Monitoring Checklist
        3. 7.6.4.3 Connection of Error Signal Output (MCU_ERRORn)
        4. 7.6.4.4 High Frequency Oscillator (MCU_OSC0) Clock Loss Detection
          1. 7.6.4.4.1 Crystal or External Oscillator Mal-function
    7. 7.7 SK Specific Circuit Implementation (Reuse)
    8. 7.8 Performing Board Level Testing During Custom Board Bring-up
      1. 7.8.1 Processor Pin Configuration Using PinMux Tool
      2. 7.8.2 Schematics Configurations
      3. 7.8.3 Connection of Supply Rails to External Pullups
      4. 7.8.4 Peripheral (Subsystem) Clock Outputs
      5. 7.8.5 General Board Bring-up and Debug
        1. 7.8.5.1 Clock Output for Board Bring-Up, Test, or Debug
        2. 7.8.5.2 Additional Information
        3. 7.8.5.3 General Board Bring-up and Debug Checklist
  11. 8 Self-Review of Custom Board Schematic Design
  12. 9 Custom Board Layout Notes (Added Near to the Schematic Sections) and General Guidelines
    1. 9.1 Layout Considerations
  13. 10Custom Board Design Simulation
    1. 10.1 DDR-MARGIN-FW
  14. 11Additional References
    1. 11.1 FAQs Covering AM64x, AM243x, AM62x, AM62Ax, AM62D-Q1, AM62Px, AM62Lx Processor Families
    2. 11.2 FAQs - Processor Product Family Wise and Sitara Processor Families
    3. 11.3 Schematics Review (Self) and Schematic Review Request (Suppliers)
    4. 11.4 Processor Attached Devices Checklist
  15. 12User's Guide Content and Usage Summary
  16. 13References
    1. 13.1  AM62P, AM62P-Q1
    2. 13.2  AM62L
    3. 13.3  AM62A7, AM62A3, AM62A7-Q1, AM62A3-Q1, AM62A1-Q1
    4. 13.4  AM62D-Q1
    5. 13.5  AM625, AM623, AM620-Q1, AM625-Q1, AM625SIP
    6. 13.6  Common for all Processor Families
    7. 13.7  Master List of Available FAQs - Processor Family Wise
    8. 13.8  Master List of Available FAQs - Sitara Processor Families
    9. 13.9  FAQs Including Software Related
    10. 13.10 FAQs for Attached Devices
  17. 14Terminology
  18. 15Revision History
4.1.1.1.1 PMIC Based Power Architecture Checklist for TPS65224x

General

Review and verify the following for the custom schematic design:

  1. Reviewed above "Common checklist for all sections" section of the user's guide
  2. PMIC selection (OPN) and configuration of the output voltages
  3. PMIC checklist for addition of required input and output capacitors including values, feedback connection, and pin connection
  4. Voltage rating of the selected capacitors considering derating
  5. Configuration of the recommended PMIC control and IO signals
  6. Connection of the required control signals for processor IO supply sequencing and slew rate control
  7. Processor I2C instance used to interface to PMIC
  8. Provision to configure processor core voltage
  9. Processor to PMIC and PMIC to processor IO interface connections
  10. Connection of analog inputs to TPS65224 PMIC ADC inputs
  11. Naming of the supply rails (indicate configured output voltage level)
  12. Net name matches (same name) for processor and attached devices IO supplies
  13. Connection of interrupt, EN/PB/VSESNSE, sleep signals and connection of the required pulls for the PMIC IOs

Schematic Review

Follow the below list for the custom schematic design:

  1. Configuration of the PMIC output to match the processor and attached devices IO supply operating voltages as per the custom board requirements
  2. The custom board PMIC implementation with the SK schematic implementation for capacitors quantity, size and values, IOs connection
  3. Connection of the PMIC buck output feedback (tie the feedback after the output bulk capacitors or remote feedback)
  4. Core voltage configuration using GPIO3 (GPIO3 High -- BUCK1,2 : 0.85V, GPIO3 Low/Floating -- BUCK1,2 : 0.75V), Connection and sequencing of VDD_CORE and VDDR_CORE
  5. Provision to configure processor core voltage (using GPIO3 for TPS65224)
  6. PMIC nRSTOUT0 slew (pullup value) when connected directly to processor MCU_PORz input (recommend using a discrete push-pull output type buffer)
  7. Connection of the required control signals for processor IO supply sequencing (load switch EN for processor and attached device IO supply voltage and provision for load switch output voltage slew rate control using external capacitor)
  8. Voltage rating of the selected capacitors considering derating (> twice the worst-case applied voltage is a commonly used guideline)
  9. Matching of the PMIC output voltage level with the supply requirements for the processor and attached devices (based on the OPN)
  10. Processor I2C instance used to interface to PMIC (Follow SK or review the required I2C instance based on the use case)
  11. Configuration of discrete DC/DC outputs and LDOs used along with the PMIC to generate additional supply rails
  12. External implementation of SD card supply switching and power switch reset logic to support UHS-I SD card
  13. Connection of analog inputs and analog input range for GPIO4 or GPIO5 (used as ADC)
  14. External LDO implementation for generating VPP supply (eFuse programming), LDO output enable (EN) control, addition of bulk and decoupling capacitors considering load current transient and provision for isolation resistor for testing the VPP supply output enable timing

Additional

  1. In case custom board design power architecture is based on TI PMIC, the recommendation is to obtain a detailed review of the implementation done with the PMIC team (business unit or product line).
  2. A 0Ω resistor or jumper is recommended at the output of the PMIC and discrete DC/DC, LDO for isolation or current measurement for the initial board build. The recommendation is to add TPs for measurement. The recommendation is to follow kelvin current sense connection for connecting TPs to 0Ω resistor or jumper.
  3. The recommendation is to connect the feedback for the PMIC buck output after the bulk capacitor. The recommendation is to connect the feedback to make sure the removal of the 0Ω resistor does not affect the PMIC operation (connect on the PMIC side of the resistor). PMIC supports connecting remote feedback near to the load.
  4. The recommendation is to show the PMIC input bulk capacitors for buck (DC/DC) inputs and VSYS separately and near to each of the pin for ease of placement and routing.
  5. To support PMIC remote voltage sensing, the recommendation is to connect the feedback pins FB_Bx of the device to the respective sense pins on the processor. Alternatively, connect the FB_Bx pin to a representative load capacitor. With differential feedback, also connect the negative feedback pin to the negative terminal of the same load capacitor.
  6. The recommendation is to review and follow the FAQs related to residual voltage.
  7. In case a non-TI PMIC is used, the recommendation for custom board designers is to review and follow the relevant processor collaterals including the processor-specific data sheet and Maximum Current Ratings application note. The recommendation is to review the Recommended Operating Conditions, Supply Slew Rate Requirements, MCU_PORz Timing Requirements, Power-Up Sequencing and Power-Down Sequencing sections of the processor-specific data sheet and confirm the selected PMIC based power architecture supports the above requirements and residual voltage (RV) check.